米6体育平台手机版

ZHCSCI5B May 2014 – July 2016 TPS544B20 , TPS544C20

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RVF|40
- MPQF268C

散热焊盘机械数据 (封装 | 引脚)

RVF|40
- QFND333E

订购信息

6 Pin Configuration and Functions

RVF Package

40-Pin LQFN with Thermal Tab

(TOP VIEW)

TPS544B20 TPS544C20 dev_SLUS69B_pinout.gif

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
ADDR0	3	O	Sets low order 3-bits of the PMBus address. Connect a resistor from this pin to AGND.
ADDR1	2	O	Sets high order 3-bits of the PMBus address. Connect a resistor from this pin to AGND.
AGNDSNS	13	G	Analog ground sense. Provides Kelvin connection point to analog ground for precise current measurement. AGNDSNS is internally connected to the thermal tab. Do not connect to the thermal tab externally. Kelvin connect back to AGND pin with a low impedance, low noise path. This kelvin connection serves as the only connection between AGND and GND.
AGND	38	G	Analog ground return for control circuitry. AGND should not be connected to the exposed thermal pad, GND or PGND, but should be Kelvin connected to the AGNDSNS pin.
BP3	27	S	Output of the 3.3-V on-board regulator. This regulator powers the controller and should be bypassed with a minimum of 100-nF capacitor to AGND.
BP6	28	S	Output of the 6-V on-board regulator. This regulator powers the driver stage of the controller and should be bypassed with a 4.7-µF ceramic capacitor to GND.
BOOT	7	S	Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from this pin to the SW pins.
BPEXT	30	I	External BP voltage for BP crossover function. Bypass with a 4.7-µF ceramic capacitor to GND if used.. Connect to GND if not used.
CLK	5	I	PMBus CLK pin. See PMBus specification.
CNTL	1	I	PMBus CNTL pin. See PMBus specification.
COMP	35	O	Output of the error amplifier. This regulates the D-CAP and D-CAP2 valley voltage reference for output regulation and should be bypassed with a 10-nF capacitor to AGND.
DATA	4	I/O	PMBus DATA pin. See PMBus specification.
DIFFO	33	O	Output of the differential sense amplifier.
FB	34	I	Feedback pin for the control loop. Regulates to a nominal 600 mV if there is no trim applied to the device using VREF_TRIM.
GND	14	G	Power stage ground return.
	15
	16
	17
	18
	19
	20
PGND	26	G	Power ground return for controller device. Connect to GND at the thermal tab with a minimum 8 mil wide PCB trace
PGOOD	36	O	Power good output. Open drain output that floats up when the device is operating and in regulation. Any fault condition causes this pin to pull low.
RT	40	O	Frequency-setting resistor. Connect a resistor from this pin to AGND to program the switching frequency.
SMBALERT	6	O	SMBus alert pin. See SMBus specification.
SW	8	O	Switched power output of the device. Connect the output averaging filter and bootstrap capacitor to this group of pins.
	9
	10
	11
	12
MODE	39	I	D-CAP and D-CAP2 control mode selection pin. Connect to BP3 for D-CAP2 mode control. Connect to AGND for D-CAP mode control.
TSNS	37	O	External temperature sense signal input. TSNS can be connected to AGND to disable external temperature measurement.
VDD	29	I	Input Voltage for analog control circuitry. Bypass with a 0.1-µF to 1.0-µF capacitor to GND (thermal pad or GND pins) or through a dedicated connection to AGNDSNS. The VDD voltage is also used for input feed-forward, ON-time generation and High Side Over Current (HSOC). VIN and VDD must be at the same voltage for accurate short circuit protection.
VIN	21	I	Input power to the power stage. Bypass High-Frequency bypassing with multiple ceramic capacitors to GND is critical. See Layout Recommendations
	22
	23
	24
	25
VOUTS+	31	I	Output voltage sensing, positive side. This sensing provides remote sensing for PMBus reporting and the voltage control loop. Connect to V_OUT at desried regulation point through < 100-Ω resistor. Route with GND to VOUT- using coupled differential pair PCB routing.
VOUTS–	32	I	Output voltage sensing, negative or common side. This sensing provides remote sensing for PMBus reporting and the voltage control loop. Connect to Ground at desried regulation point through < 100-Ω resistor. Route with V_OUT to VOUT+ using coupled differential pair PCB routing.
Thermal tab			Package thermal tab. Connect to GND. The thermal tab must have adequate solder coverage for proper operation.

(1) I = Input, O = Output, P = Supply, G = Ground