8.3.1 Turn-On and Turn-Off Delay and Sequencing

The TPS544C20 and TPS544B20 devices provide many sequencing options. Using the ON_OFF_CONFIG command, the device can be configured to start up when the input voltage is above the undervoltage lockout (UVLO) threshold, or to additionally require a signal on the CNTL pin and/or receive an update to the OPERATION command according to the PMBus protocol. When the gating signal as specified by ON_OFF_CONFIG command is asserted, a programmable turn-on delay can be set with the TON_DELAY command to delay the start of regulation. Similarly, a programmable turn-off delay can be set with the TOFF_DELAY command to delay the stop of regulation once the gating signal is de-asserted. Delay times are specified as an integer multiple of the soft-start time.

When the output voltage remains within the PGOOD window after the start-up period, PGOOD is released, and rises to an externally supplied logic level. The PGOOD signal can be connected to the CNTL pin of another device to provide additional controlled turn-on and turn-off sequencing.

Figure 20 shows control of the start-up and shutdown operations of the device, when the device is configured to respond to a logical AND of both CNTL and the OPERATION command. The device can also be configured to respond to only the CNTL signal, only the OPERATION command, or to convert power whenever VDD is greater than the VIN_ON command value setting.

1. Bit 7 of OPERATION is used to control power conversion. Other bits in this register control output voltage margining.

Figure 20. Turn-On Controlled By Both Operation1 and Control

8.3.2 Pre-Biased Output Start-Up

The TPS544C20 and TPS544B20 devices prevent current from discharging from the output during start-up, when a pre-biased output condition exists. No SW pulses occur until the internal soft-start voltage rises above the error amplifier input voltage (FB pin), if the output is pre-biased. When the soft-start voltage exceeds the error amplifier input, and SW pulses start, the device limits synchronous rectification time after each SW pulse with a narrow on-time. The low-side MOSFET on-time slowly increases each switching cycle until it generates 128 pulses. After 128 pulses, the synchronous rectifier runs fully complementary to the high-side MOSFET. This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage start-up and ramp-to-regulation sequences are smooth and monotonic. These devices respond to a pre-biased output over-voltage condition immediately upon power-up, even during soft-start, while disabled or below the PMBus programmable undervoltage lockout on-time (UVLO_ON).

The combination of D-CAP and D-CAP2 mode control and the limited on-time of the low-side MOSFET during the pre-bias sequence allows these devices to operate at low switching frequencies for the first 128 switching cycles, after which the device operates using pseudo-constant frequency.

8.3.3 Voltage Reference

A 600-mV bandgap cell connects internally to the non-inverting input of the error amplifier. The 0.5% tolerance on the reference voltage allows for a power supply design that yields very high DC accuracy.

8.3.4 Differential Remote Sense and Output Voltage Setting

The TPS544C20 and TPS544B20 devices implement a differential remote sense amplifier to provide excellent load regulation by cancelling IR-drop in high current applications. The VOUTS+ and VOUTS– pins should be kelvin-connected to the output capacitor bank directly at the load, and routed back to the device as a tightly coupled differential pair. Ensure that these traces are isolated from fast switching signals and high current paths on the final PCB layout to mitigate differential-mode noise. Optionally, use a small coupling capacitor (330-pF typical) between the VOUTS+ and VOUTS– pins to improve noise immunity. The output of the differential remote sense amplifier (DIFFO) sets the output voltage.

A voltage divider from the DIFFO pin to the FB pin sets the nominal output voltage. The output voltage must be divided down to the nominal reference voltage of 600 mV. The feedback voltage can be adjusted within –30% and +10% from the nominal 600 mV using PMBus commands, allowing the output voltage to vary by the same percentage. During the power-up sequence, the feedback reference is 600 mV plus any offset generated by the MARGIN command or VREF_TRIM command values which were previously stored in EEPROM. The initial output voltage equals the feedback voltage scaled by the divider ratio. See the PMBus Output Voltage Adjustment section for further details.

The device enables telemetry by digitizing the voltage at the DIFFO pin, averaging it to reduce measurement noise, and storing it in the READ_VOUT (8Bh) register.

Figure 21. Output Voltage Setting

Equation 1 calculates the nominal output voltage. R1 can be arbitrarily selected to be 10-kΩ, with R_BIAS being scaled appropriately.

Equation 1.

8.3.5 PMBus Output Voltage Adjustment

The nominal output voltage of the converter can be adjusted by changing the feedback voltage, V_FB, using the VREF_TRIM command. The adjustment range is between –20% and +10% from the nominal output voltage. This command adjusts the final output voltage of the converter to a high degree of accuracy, without relying on high-precision feedback resistors. The resolution of the adjustment is 7 bits, with a resulting minimum step size of approximately 2 mV, or 0.4%. The total output voltage adjustable range, including MARGIN and VREF_TRIM is –30% to + 10%.

The TPS544C20 and TPS544B20 devices allow simple output voltage margin testing, by applying a either a positive or negative offset to the feedback voltage. The STEP_VREF_MARGIN_HIGH and STEP_VREF_MARGIN_LOW commands control the size of the applied high or low offset respectively. The OPERATION command toggles the converter between three states:

• Margin none (no output margining). See Equation 2
• Margin high. See Equation 3
• Margin low. See Equation 4

Equation 2.

Equation 3.

Equation 4.

Figure 22 shows an example of the VREF_TRIM and margin timing.

Figure 22. VREF_TRIM and Margin Example

The nominal 600-mV FB pin references the OV fault, UV fault, and PGOOD limits, as defined by PCT_VOUT_FAULT_PG_LIMIT command, regardless of VREF_TRIM or output margining. These limits remain fixed percentages of the nominal 600 mV reference, regardless of output margining.

8.3.6 Switching Frequency

A resistor from the RT pin to AGND establishes the switching frequency during the power-up sequence. To ensure proper detection, select a resistor with 1% tolerance from Table 2.

The TPS544B20 and TPS544C20 devices detect values that are out-of-range on the RT pin. If the device detects that RT pin has an out-of-range resistance connected to it, the device selects a frequency setting of either 250 kHz (if the resistance is less than 5 kΩ) or 1 MHz (if the resistance is greater than 300 kΩ). In this case, the device also asserts the IVFREQ bit in STATUS_MFR_SPECIFIC. Once VDD is applied, the frequency latches in memory and RT pin deactives until BP6 falls below V_BP6UV. When the device has completed the Power-on-reset sequence, it latches the frequency in memory and deactivates the RT pin until the BP6 voltage falls below the BP6 undervoltage threshold setting.

8.3.7 Soft-Start

To control the inrush current needed to charge the output capacitors during the start-up sequence, the TPS544C20 and TPS544B20 devices implement a soft-start time. When the device is enabled, the feedback reference voltage, V_REF, rises from 0 V to its final value (including output margining or VREF_TRIM value) at a slew rate defined by the TON_RISE command. The slew rate needed to increase the reference voltage from 0 V to 600 mV at each given rise time defines the specified rise times. During the soft-start period, the error amplifier operates as a unity-gain buffer to force the COMP pin voltage to track the internal reference and minimize the offset between the internal reference and the output voltage. Because D-CAP mode or D-CAP2 mode control regulates the valley voltage, the average output voltage can exceed the final regulation voltage several millivolts at the end of the soft-start period See Figure 23.

Figure 23. Soft-Start

8.3.8 Linear Regulators BP3 and BP6

Two on-board linear regulators provide suitable power for the internal circuitry of the devices. Externally bypass pins BP3 and BP6 for the converter to function properly. BP3 requires a minimum of 100 nF of capacitance connected to AGND. BP6 should be bypassed to GND with a 4.7-µF capacitor.

These devices allow the use of an internal regulator to power other circuits. Ensure that external loads placed on the regulators do not adversely affect operation of the controller. Avoid loads with heavy transient currents that can affect the regulator outputs. Transient voltages on these outputs can result in noisy or erratic operation. Observe the current limits. Shorting the BP3 pin to GND can damage the BP3 regulator. The BP3 regulator input comes from the BP6 regulator output. The BP6 regulator can supply 120 mA of current and the total current drawn from both regulators must be less than 120 mA. This total current includes the device operating current (I_VDD) plus the gate-drive current required to drive the power MOSFETs.

8.3.9 External Bypass (BPEXT)

The BPEXT pin provides an external bypass of the internal BP6 regulator when the application includes an external bias supply between 4.5 V and 6.5 V. Using an external supply reduces the power dissipation in these devices and can slightly improve system efficiency. If the input voltage is less than the UVLO threshold, or if the voltage on the BPEXT pin is lower than the switch-over voltage, V_{BPEXT(swover)}, these devices use the internal BP6 regulator. If the voltage on the BPEXT pin exceeds this switch-over voltage, then these devices disable the internal BP6 regulator and BPEXT outputs to BP6, replacing the internal linear regulator, until the voltage on the BPEXT pin falls by the BPEXT switch-over hysteresis amount, V_HYS(swover). If the application does not require the BPEXT function, connect the BPEXT pin to GND.

Figure 24. BP External

Figure 25. BP Crossover Diagram

8.3.10 Current Monitoring and Low-Side MOSFET Overcurrent Protection

The TPS544C20 and TPS544B20 devices sense average output current using an internal sensefet. A sensefet conducts a scaled-down version of the power-stage current. Sampling this current in the middle of the low-side drive signal determines the average output current. This architecture achieves excellent current monitoring and better overcurrent threshold accuracy than inductor DCR current sensing with minimal temperature variation and no dependence on power loss in a higher DCR inductor. This enables the use of lower DCR inductors to improve efficiency. Use the IOUT_CAL_OFFSET command to improve current sensing and overcurrent accuracy by removing board layout-related systematic errors post assembly. The devices continually digitize the sensed output current, and average it to reduce measurement noise. The devices then store the current value in the read-only READ_IOUT register, enabling output current telemetry.

Figure 26. Sensefet Average Current Sensing and Low-Side Overcurrent Protection

The TPS544C20 and TPS544B20 devices also implement low-side MOSFET overcurrent protection with programmable fault and warning thresholds. The IOUT_OC_FAULT_LIMIT and commands set the low-side overcurrent thresholds.

As shown in Figure 26, if an overcurrent event is detected in a given switching cycle, the device increments an overcurrent counter. When the device detects seven consecutive low-side overcurrent events, the converter responds, flagging the appropriate status registers, triggering SMBALERT if it is not masked, and entering either continuous restart hiccup, or latch-off according to the IOUT_OC_FAULT_RESPONSE command. In continuous restart hiccup mode, the devices implement a time-out function that occurs after seven soft-start cycles; followed by a normal soft-start attempt. When the overcurrent fault clears, normal operation resumes, otherwise, the device detects overcurrent and the process repeats.

8.3.11 High-Side MOSFET Short-Circuit Protection

The TPS544B20 and devices also implement a fixed high-side MOSFET overcurrent (HSOC) protection to limit peak current, and prevent inductor saturation in the event of a short circuit. The devices detect an overcurrent event by sensing the voltage drop across the high-side MOSFET when it is on. If the peak current reaches the HSOC level on any given cycle, the cycle terminates to prevent the current from increasing any further. For accurate high-side MOSFET overcurrent protection, the VIN and VDD pins must be at the same voltage; split rail operation is not supported.

8.3.12 Over-Temperature Protection

An internal temperature sensor protects the devices from thermal runaway. The internal thermal shutdown threshold, T_SD, is fixed at 145°C typical. When the devices sense a temperature above T_SD, an over-temperature fault internal (OTFI) is flagged, and power conversion stops until the sensed junction temperature falls by the thermal shutdown hysteresis amount, T_HYST, (25°C typical). Additionally, the OTFI bit in STATUS_MFR_SPECIFIC setting indicates when the devices detect an internal over-temperature event.

The TPS544C20 and TPS544B20 devices also provide programmable external over-temperature fault and warning thresholds using measurements from an external temperature sensor connected on the TSNS pin. The temperature sensor circuit applies two bias currents to an external NPN transistor, and measures ΔV_BE to infer the junction temperature of the sensor. The TPS544C20 and TPS544B20 devices are designed to use a standard 2N3904 NPN transistor as a temperature sensor. Other sensors may be used, but the devices assume an ideality factor, n, of 1.008 for use with the 2N3904. The devices then digitize the result and compare it to the user-configured over-temperature fault and warning thresholds. When an external over-temperature fault (OTF) is detected, power conversion stops until the sensed temperature falls by 20°C. The READ_TEMPERATURE_2 (8Eh) register is continually updated with the digitized temperature measurement, enabling temperature telemetry. The OT_FAULT_LIMIT (4Fh) and OT_WARN_LIMIT (51h) commands set the PMBus over-temperature fault and warning thresholds. When an overtemperature event is detected, the device sets the appropriate flags in STATUS_TEMPERATURE (7Dh) and triggers SMBALERT if it is not masked.

TI recommends routing a differential pair of AGND and TSNS from the TPS544B20 and TPS544C20 to the collector-base and emitter terminals of the 2N3904. Include a 330-pF capacitor between the TSNS and AGND pair traces to reduce temperature measurement noise and associated error. Implement the option to disable external temperature sensing by terminating TSNS to AGNS with a 0-Ω resistor. This termination forces the external temperature measurement to –40°C, and prevents external over-temperature faults tripping. The internal temperature sensor, and internal over-temperature fault remain enabled regardless of the TSNS pin termination.

Figure 27. Over-Temperature Protection

8.3.13 Input Undervoltage Lockout (UVLO)

The TPS544C20 and TPS544B20 devices provide flexible user adjustment of the undervoltage lockout threshold and hysteresis. Two PMBus commands, VIN_ON (35h) and VIN_OFF (36h) allow the user to set these input voltage turn-on and turn-off thresholds independently, with a minimum of 4-V turn-off to a maximum 16-V turn-on. See the command descriptions for more details.

8.3.14 Output Overvoltage and Undervoltage Protection

The TPS544C20 and TPS544B20 devices include both output overvoltage protection (OVP) and output undervoltage (UVP) protection. The devices compare the FB pin voltage to internal selectable pre-set voltages, as defined by the PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h) command. As the output voltage rises or falls from the nominal voltage, the FB voltage tracks a direct divider ratio of the output voltage. If the FB voltage rises above the OVP threshold, the device terminates normal switching, declares an OV fault and turns on the low-side MOSFET to discharge the output capacitor and prevent further increases in the output voltage. If the FB voltage falls below the OVP threshold, the low-side FET turns off and normal switching resumes.

If the FB voltage falls below the undervoltage protection level after soft-start sequence has completed, the device terminates normal switching and forces both the high-side and low-side MOSFETs off, and awaits an external reset or begins a hiccup time-out delay prior to restart, depending on the value of the IOUT_OC_FAULT_RESPONSE (47h) command. The output undervoltage response is shared with the over-current fault response.

8.3.15 Fault Protection Responses

Table 3 summarizes the various fault protections and associated responses.

8.3.16 PMBus General Description

Timing and electrical characteristics of the PMBus specification can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.1 available at http://pmbus.org. The TPS544B20 and TPS544C20devices support both the 100-kHz and 400-kHz bus timing requirements. The TPS544B20 and TPS544C20 devices do not implement clock stretching when communicating with the master device.

Communication over the PMBus interface can support Packet Error Checking (PEC) if desired. If the PMbus host supplies clock (CLK pin) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used.

These devices support a subset of the commands in the PMBus 1.1 Power Management Protocol Specification. See the Supported PMBus Commands section for more information.

The devices also support the SMBALERT response protocol. The SMBALERT response protocol is a mechanism by which a slave device (such as the TPS544C20 device or the TPS544B20 device) can alert the master device that it is available for communication. The master device processes this event and simultaneously accesses all slave devices on the bus (that support the protocol) through the alert response address (ARA). Only the slave device that caused the alert acknowledges this request. The host device performs a modified receive byte operation to ascertain the slave devices address. At this point, the master device can use the PMBus status commands to query the slave device that caused the alert. By default, these devices implement the auto alert response, a manufacturer specific improvement to the SMBALERT response protocol, intended to mitigate the issue of bus hogging. See the Auto ARA (Alert Response Address) Response section for more information. For more information on the SMBus alert response protocol, see the System Management Bus (SMBus) specification.

The devices contain non-volatile memory that stores configuration settings and scale factors. However, the devices do not save the settings programmed into this non-volatile memory. The STORE_USER_ALL (15h) command must be used to commit the current settings to non-volatile memory as device defaults. Settings available for storage in NVM are noted in their detailed descriptions.

8.3.17 PMBus Address

The PMBus specification requires that each device connected to the PMBus have a unique address on the bus. The TPS544B20 and TPS544C20 devices each have 64 possible addresses (0 through 63 in decimal) that can be assigned by connecting resistors from the ADDR0 and ADDR1 pins to AGND. The address is set in the form of two octal (0-7) digits, one digit for each pin. ADDR1 is the high order digit and ADDR0 is the low-order digit. These address selection resistors must be 1% tolerance or better. Using resistors other than the recommended values can result in devices responding to adjacent addresses.

The E96 series resistors recommended for each digit value are shown in Table 4.

The devices detect values that are out-of-range on the ADDR0 and ADDR1 pins. If the device detects that either pin has an out-of-range resistance connected to it, the device continues to respond to PMBus commands, but does so at address 127, which is outside of the possible programmed addresses. It is possible but not recommended to use the device in this condition, especially if other devices are present on the bus or if another device could possibly occupy the 127 address.

The device reserves certain addresses in the I²C address space for special functions. The PMBus protocol allows the address of the device to respond to these addresses. The user is responsible for knowing which of these reserved addresses are in use in a system and for setting the address of the device accordingly so as not to interfere with other system operations.

8.3.18 PMBus Connections

The TPS544B20 and TPS544C20 devices support both the 100-kHz and 400-kHz bus speeds. Connection for the PMBus interface should follow the specification given in section 3.1.3 High-Power DC in the SMBus specification V2.0 for the 400-kHz bus speed or the 3.1.2 Low Power DC section. The complete SMBus specification is available from the SMBus web site, smbus.org.

8.3.19 Auto ARA (Alert Response Address) Response

By default, the TPS544B20 and TPS544C20 devices implement the auto alert response, a manufacturer specific improvement to the standard SMBALERT response protocol defined in the SMBus specification. The auto alert response is designed to prevent SMBALERT monopolizing in the case of a persistent fault condition on the bus. The user can choose to disable the auto ARA response, and use the standard SMBALERT response as defined in the SMBus specification, by using bit 8 of the MASK_SMBALERT (MFR_SPECIFIC_23) (E7h) command.

In the case of a fault condition, the slave device experiencing the fault pulls down the shared SMBALERT line, to alert the host that a fault condition has occurred. To establish which slave device has experienced the fault, the host issues a modified receive byte operation to the alert response address (ARA), to which only the slave device pulling down on SMBALERT should respond. The SMBus protocol provides a method for address arbitration in the case that multiple slave devices on the same bus are experiencing fault conditions. Once the host has established the address of the offending device, it must take any necessary action to release the SMBALERT line. For more information on the standard SMBus alert response protocol, see the System Management Bus (SMBus) specification.

In the case of a non-persistent fault (for example, a single-time event, such as an invalid command or data byte), the host can ascertain the address of the slave device experiencing a fault using the standard ARA response, and simply issue CLEAR_FAULTS (03h) to release the SMBALERT line, and resume normal operation. However, in the case of a persistent fault (i.e. one which remains active for some time, such as a short-circuit, or thermal shutdown), once the device issues a CLEAR_FAULTS (03h) command, the fault immediately re-triggers, and SMBALERT continues to be pulled low. In this case, the device holds low the SMBALERT line until the host masks the SMBALERT line using MASK_SMBALERT (MFR_SPECIFIC_23) (E7h) and then issues the CLEAR_FAULTS (03h) command. Because the SMBALERT line remains low, the host cannot be alerted to other fault conditions on the bus until it clears SMBALERT. This situation is known as bus hogging. Figure 28 and Figure 29 illustrate an example of this response.

.

Figure 28. Example Standard ARA Response to Non-Persistent Fault

.

Figure 29. Example Standard ARA Response to a Persistent Fault

.

In order to mitigate the problem of bus hogging, these devices implement the Auto ARA response. When Auto ARA is enabled, the devices release SMBALERT automatically after successfully responding to access from the host at the alert response address. In this case, even when a device is experiencing a persistent fault, it does not hold the SMBALERT line low following successful notification of the host, and the host can be alerted to other faults on the bus in the normal manner. Examples of the auto ARA response are illustrated in Figure 30 and Figure 31.

Figure 30. Example Auto ARA Response to Non-Persistent Fault

Figure 31. Example Auto ARA Response to Persistent Fault

8.4.1 Continuous Conduction Mode

The TPS544B20 and TPS544C20 devices operate in continuous conduction mode (CCM) at a fixed frequency, regardless of the output current. For the first 128 switching cycles, the low-side MOSFET on-time is slowly increased to prevent excessive current sinking when the device starts up with a pre-biased output. Following the first clock 128 cycles, the low-side MOSFET and the high-side MOSFET on-times are fully complementary.

8.4.2 Operation with Internal BP6 Regulator

The TPS544B20 and TPS544C20 devices include an internal linear regulator to supply bias for internal logic and the power MOSFET drivers. The BP6 regulator steps down the VDD voltage to approximately 6.5 V when V_VDD is above 6.5 V, or operates with a maximum of 100-mV dropout when V_VDD is less than 6.5 V. In this case, the BPEXT pin should be connected to GND.

8.4.3 Operation with BP External

The TPS544B20 and TPS544C20 devices can operate with an externally supplied voltage applied on the BPEXT pin to bypass the BP6 regulator, which powers the MOSFET drivers. Using BP External reduces the power dissipation inside the device, and leads to a small gain in overall efficiency. In this case, the BP6 regulator should be bypassed as normal, but the BPEXT pin should also have a minimum of 2.2-µF bypass capacitance relative to GND. See External Bypass (BPEXT) for more information.

8.4.4 Operation with CNTL Signal Control

According to the value in the ON_OFF_CONFIG register, The TPS544B20 and TPS544C20 devices can be commanded to use the CNTL pin to enable or disable regulation, regardless of the state of the OPERATION command. The minimum input high threshold for the CNTL signal is 2.1 V, and the maximum input low threshold for the CNTL signal is 0.8 V. The CNTL pin can be configured as either active high or active low (inverted) logic.

8.4.5 Operation with OPERATION Control

According to the value in the ON_OFF_CONFIG register, these devices can be commanded to use the OPERATION command to enable or disable regulation, regardless of the state of the CNTL signal.

8.4.6 Operation with CNTL and OPERATION Control

According to the value in the ON_OFF_CONFIG register, these devices can be commanded to require both a signal on the CNTL pin, and the OPERATION command to enable or disable regulation.

8.4.7 Operation with Output Margining

The OPERATION command can be used to toggle the device between three states:

• Margin none
• Margin low
• Margin high

In the margin none state, the feedback reference, V_REF, is equal to the nominal 600-mV reference, plus any offset defined by the VREF_TRIM command. In the margin low state, a negative offset defined by the STEP_VREF_MARGIN_LOW command is applied to the feedback reference, moving the converter output voltage down by an equivalent percentage. In the margin high state, a positive offset defined by the STEP_VREF_MARGIN_HIGH command is applied to the feedback reference, moving the converter output voltage up by an equivalent percentage. See the PMBus Output Voltage Adjustment section for more information.

8.5.1 Supported PMBus Commands

The commands listed in the Table 5 section are implemented as described to conform to the PMBus 1.1 specification. It also shows default behavior and register values.

8.6.1 OPERATION (01h)

The OPERATION command turns the device output on or off in conjunction with input from the CNTL signal. It also sets the output voltage to the upper or lower margin voltages. The unit stays in the commanded operating mode until a subsequent OPERATION command or a change in the state of the CNTL pin instructs the device to change to another mode.

8.6.2 ON_OFF_CONFIG (02h)

The ON_OFF_CONFIG command configures the combination of CNTL pin input and serial bus commands needed to turn the unit on and off. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

8.6.3 CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status registers simultaneously. At the same time, the device negates (clears, releases) its SMBALERT output if the device is asserting SMBALERT. The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault bit is immediately reset and the host notified by the usual means.

8.6.4 WRITE_PROTECT (10h)

The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is to provide protection against accidental changes. This command is not intended to provide protection against deliberate or malicious changes to the device configuration or operation. All supported command parameters may have their parameters read, regardless of the WRITE_PROTECT settings. Write protection also prevents protected registers from being updated in the event of a RESTORE_USER_ALL. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

8.6.5 STORE_USER_ALL (15h)

The STORE_USER_ALL command stores all of the current storable register settings in the EEPROM memory as the new defaults on power up.

It is permissible to use this command while the device is switching. Note however that the device continues to switch but ignores all fault conditions until the internal store process has completed.

EEPROM programming faults cause the device to NACK and set the 'cml' bit in the STATUS_BYTE and the 'oth' bit in the STATUS_CML registers.

The following registers can be stored to EEPROM memory using STORE_USER_ALL:

• ON_OFF_CONFIG
• WRITE_PROTECT
• VIN_ON
• VIN_OFF
• IOUT_CAL_OFFSET
• IOUT_OC_FAULT_LIMIT
• IOUT_OC_WARN_LIMIT
• IOUT_OC_FAULT_RESPONSE
• OT_FAULT_LIMIT
• OT_WARN_LIMIT
• TON_RISE
• MFR_SPECIFIC_00
• VREF_TRIM
• STEP_VREF_MARGIN_HIGH
• STEP_VREF_MARGIN_LOW
• PCT_VOUT_FAULT_PG_LIMIT
• SEQUENCE_TON_TOFF_DELAY
• OPTIONS
• MASK_SMBALERT

8.6.6 RESTORE_USER_ALL (16h)

The RESTORE_USER_ALL command restores all of the storable register settings from EEPROM memory.

Do not use this command while the device is actively switching, this causes the device to stop switching and the output voltage to fall during the restore event. Depending on loading conditions, the output voltage could reach an undervoltage level and trigger an undervoltage fault response if programmed to do so. The command can be used while the device is switching, but it is not recommended as it results in a restart that could disrupt power sequencing requirements in more complex systems. It is strongly recommended that the device be stopped before issuing this command.

8.6.7 CAPABILITY (19h)

The CAPABILITY command provides a way for a host system to determine some key capabilities of this PMBus device.

The default values indicate that the device supports Packet Error Checking (PEC), a maximum bus speed of 400 kHz (SPD) and the SMBus Alert Response Protocol using SMBALERT.

8.6.8 VOUT_MODE (20h)

The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the device uses the Linear or Direct modes for output voltage related commands. The 5-bit parameter sets the exponent value for the linear data mode. The mode and exponent parameters are fixed and do not permit the user to change the values.

8.6.9 VIN_ON (35h)

The VIN_ON command sets the value of the input voltage at which the unit should start operation assuming all other required startup conditions are met. Values are mapped to the nearest supported increment. Values outside the supported range are treated as invalid data and cause the device set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers. The value of VIN_ON remains unchanged on an out-of-range write attempt. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The supported VIN_ON values are shown in Table 6:

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5-bit exponent and an 11-bit mantissa. The four most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

8.6.10 VIN_OFF (36h)

The VIN_OFF command sets the value of the input voltage at which the unit should stop operation. Values are mapped to the nearest supported increment. Values outside the supported range is treated as invalid data and causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers. The value of VIN_OFF remains unchanged during an out-of-range write attempt. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The supported VIN_OFF values are shown in Table 7:

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the cml bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5 bit exponent and an 11 bit mantissa. The 4 most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

8.6.11 IOUT_CAL_OFFSET (39h)

The IOUT_CAL_OFFSET is used to compensate for offset errors in the READ_IOUT results and the IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT thresholds. The units are amperes. The default setting is 0 A. The resolution of the argument for this command is 62.5 mA and the range is +3937.5 mA to -4000 mA. Values written outside of this range alias into the supported range. This occurs because the read-only bits are fixed. The exponent is always –4 and the 5 msb bits of the Mantissa are always equal to the sign bit. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

8.6.12 IOUT_OC_FAULT_LIMIT (46h)

The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an overcurrent fault condition. The IOUT_OC_FAULT_LIMIT should be set equal to or greater than the IOUT_OC_WARN_LIMIT. Writing a value to IOUT_OC_FAULT_LIMIT less than IOUT_OC_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert SMBALERT. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The IOUT_OC_FAULT_LIMIT takes a two-byte data word formatted as shown below:

8.6.12.2 Mantissa

The upper four bits are fixed at 0.
The lower seven bits are programmable.

The actual output current for a given mantissa and exponent is shown in Equation 5.

Equation 5.

The default values and allowable ranges for each device are summarized below:

DEVICE	OC_FAULT_LIMIT			UNIT
	MIN	DEFAULT	MAX
TPS544C20	5	39	45	A
TPS544B20	5	26	30	A

8.6.13 IOUT_OC_FAULT_RESPONSE (47h)

The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an IOUT_OC_FAULT_LIMIT or a VOUT undervoltage (UV) fault. The device also:

• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT or POUT bit in the STATUS_WORD
• Sets the IOUT OC Fault bit in the STATUS_IOUT register
• Notifies the PMBus host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_USER command.

8.6.14 IOUT_OC_WARN_LIMIT (4Ah)

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the over-current detector to indicate an over-current warning. When this current level is exceeded the device:

• Sets the OTHER bit in the STATUS_BYTE
• Sets the IOUT or POUT bit in the STATUS_WORD
• Sets the IOUT overcurrent Warning (OCW) bit in the STATUS_IOUT register, and
• Notifies the host by asserting SMBALERT

The IOUT_OC_WARN_LIMIT threshold should always be set to less than or equal to the IOUT_OC_FAULT_LIMIT. Writing a value to IOUT_OC_WARN_LIMIT greater than IOUT_OC_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert SMBALERT. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The IOUT_OC_WARN_LIMIT takes a two byte data word formatted as shown below:

8.6.14.2 Mantissa

The upper four bits are fixed at 0.
Lower seven bits are programmable.

The actual output warning current level for a given mantissa and exponent is:

Equation 6.

The default values and allowable ranges for each device are summarized below:

DEVICE	OC_WARN_LIMIT			UNIT
	MIN	DEFAULT	MAX
TPS544C20	4	30	45	A
TPS544B20	4	20	30	A

8.6.15 OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-temperature fault condition, when the sensed temperature from the external sensor exceeds this limit. Upon triggering the over-temperature fault, the device takes the following actions:

• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the OT Fault bit in the STATUS_TEMPERATURE
• Notifies the host by asserting SMBALERT

Once the over-temperature fault is tripped, the output is latched off until the external sensed temperature falls 20°C from the OT_FAULT_LIMIT, at which point the output goes through a normal startup (soft-start).

The OT_FAULT_LIMIT must always be greater than the OT_WARN_LIMIT. Writing a value to OT_FAULT_LIMIT less than or equal to OT_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as asserts SMBALERT. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The OT_FAULT_LIMIT takes a two byte data word formatted as shown below.

8.6.16 OT_WARN_LIMIT (51h)

The OT_ WARN _LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-temperature warning condition, when the sensed temperature from the external sensor exceeds this limit. Upon triggering the over-temperature warning, the device takes the following actions:

• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the OT Warning bit in the STATUS_TEMPERATURE
• Notifies the host by asserting SMBALERT

Once the over-temperature warning is tripped, the warning flag is latched until the external sensed temperature falls 20°C from the OT_WARN_LIMIT.

The OT_WARN_LIMIT must always be less than the OT_FAULT_LIMIT. Writing a value to OT_WARN_LIMIT greater than or equal to OT_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert SMBALERT. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The OT_WARN_LIMIT takes a two byte data word formatted as shown below:

8.6.17 TON_RISE (61h)

The TON_RISE command sets the time in ms, from when the reference starts to rise until the voltage has entered the regulation band. It also determines the rate of the transition of the reference voltage (either due to VREF_TRIM or STEP_VREF_MARGIN_x commands) when this transition is executed during the soft-start period. There are several discrete settings that this command supports. Commanding a value other than one of these values results in the nearest supported value being selected.

The supported TON_RISE times over PMBus are shown in Table 8:

A value of 0 ms instructs the unit to bring its output voltage to the programmed regulation value as quickly as possible. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The TON_RISE command is formatted as a linear mode two’s complement binary integer.

8.6.18 STATUS_BYTE (78h)

The STATUS_BYTE command returns one byte of information with a summary of the most critical device faults.

A "1" in any of these bit positions indicates that:

8.6.19 STATUS_WORD (79h)

The STATUS_WORD command returns two bytes of information with a summary of the device fault and warning conditions. The low byte is identical to the STATUS_BYTE above. The additional byte reports the warning conditions for output overvoltage and overcurrent, as well as the power good status of the converter.

A "1" in any of the low byte (STATUS_BYTE) bit positions indicates that:

A "1" in any of the high byte bit positions indicates that:

8.6.20 STATUS_VOUT (7Ah)

The STATUS_VOUT command returns one byte of information relating to the status of the output voltage related faults. The only bits of this register supported are:

• VOUT_OV Fault
• VOUT_UV Fault

A "1" in any of these bit positions indicates that:

8.6.21 STATUS_IOUT (7Bh)

The STATUS_IOUT command returns one byte of information relating to the status of the output current related faults. The only bits of this register supported are:

• IOUT_OC Fault
• IOUT_OC Warning

A "1" in any of these bit positions indicates that:

8.6.22 STATUS_TEMPERATURE (7Dh)

The STATUS_TEMPERATURE command returns one byte of information relating to the status of the external temperature related faults. The only bits of this register supported are:

• OT Fault
• OT Warning

A "1" in any of these bit positions indicates that:

8.6.23 STATUS_CML (7Eh)

The STATUS_CML command returns one byte of information relating to the status of the converter’s communication related faults. The bits of this register supported by the this family of devices are:

• Invalid or Unsuppported Command
• Invalid or Unsupported Data
• Packet Error Check Failed
• Memory Fault Detected
• Other Communication Fault.

A "1" in any of these bit positions indicates that:

8.6.24 STATUS_MFR_SPECIFIC (80h)

The STATUS_MFR_SPECIFIC command returns one byte of information relating to the status of manufacturer-specific faults or warnings.

A "1" in any of these bit positions indicates that:

8.6.25 READ_VOUT (8Bh)

The READ_VOUT commands returns two bytes of data in the linear data format that represent the output voltage of the controller. The output voltage is sensed at the remote sense amplifier output pin so voltage drop to the load is not accounted for. The data format is as shown below:

The setting of the VOUT_MODE affects the results of this command as well. In this family of devices, VOUT_MODE is set to linear mode with an exponent of –9 and cannot be altered. The output voltage calculation is shown in Equation 7.

Equation 7.

8.6.26 READ_IOUT (8Ch)

The READ_IOUT commands returns two bytes of data in the linear data format that represent the output current of the controller. The average output current is sensed according to the method described in Low-Side MOSFET Current Sensing and Overcurrent Protection. The data format is as shown below:

The device scales the output current before it reaches the internal analog to digital converter so that resolution of the output current read is 62.5 mA. The maximum value that can be reported is 64 A. The user must set the IOUT_CAL_OFFSET parameter correctly in order to obtain accurate results. Calculate the output current using Equation 8.

Equation 8.

8.6.27 READ_TEMPERATURE_2 (8Eh)

The READ_TEMPERATURE_2 command returns the external temperature in degrees Celsius of the current channel.

8.6.28 PMBUS_REVISION (98h)

The PMBUS_REVISION command returns a single, unsigned binary byte that indicates that these devices are compatible with the 1.1 revision of the PMBus specification.

8.6.29 MFR_SPECIFIC_00 (D0h)

The MFR_SPECIFIC_00 register is dedicated as a user scratch pad.

The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

8.6.30 VREF_TRIM (MFR_SPECIFIC_04) (D4h)

The VREF_TRIM command applies a fixed offset voltage to the reference voltage. It is most typically used to trim the output voltage at the time the PMBus device is assembled into the final application design. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

the settings of the VOUT_MODE command determine the effect of VREF_TRIM command. In this device, the VOUT_MODE is fixed to Linear with an exponent of –9 (decimal).

Equation 9.

The maximum trim ranges between –20% to +10% of the nominal reference voltage (600 mV) in 2 mV steps. Permissible values range from –120 mV to +60 mV. If a value outside this range is given with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible reference voltage adjustment range is –180 mV to +60 mV (-30% to +10%). If a value outside this range is given with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is executed during the soft-start period. Any transition in the reference voltage after soft-start is complete occurs at the slew rate defined by the slowest soft-start time, or 0.067 mV/µs. For example, a trim which moves the reference by 10%, occurs in approximately 900 µs.

8.6.31 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)

The STEP_VREF_MARGIN_HIGH command sets the target voltage which the reference voltage changes to when the OPERATION command is set to "Margin High". The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the VOUT_MODE is fixed to Linear with an exponent of –9 (decimal). The actual reference voltage commanded by a margin high command can be found by:

Equation 10.

The margin high range is between 0% and 10% of the nominal reference voltage (600 mV) in 2-mV steps. Permissible values range from 0 mV to 60 mV. If a value outside this range is given with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible reference voltage adjustment range is –180 mV to 60 mV (-30% to 10%). If a value outside this range is given with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is executed during soft-start. Any transition in the reference voltage after soft-start is complete occurs at the slew rate defined by the slowest soft-start time, or 0.067 mV/µs. For example, a trim which moves the reference by 10%, occurs in approximately 900 µs.

The default value of STEP_VREF_MARGIN_HIGH is 30 (dec), corresponding to a default margin high voltage of 60 mV (+10%) .

8.6.32 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)

The STEP_VREF_MARGIN_LOW command sets the target voltage which the reference voltage changes to when the OPERATION command is set to Margin Low. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the VOUT_MODE is fixed to Linear with an exponent of –9 (decimal). Equation 11 shows the actual output voltage commanded by a margin high command.

Equation 11.

The margin low ranges between –20% and 0% of the nominal reference voltage (600 mV) in 2-mV steps. Permissible values range from –120 mV to 0 mV. If a value outside this range is given with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible reference voltage adjustment range is –180 mV to 60 mV (–30% to +10%). If a value outside this range is given with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is executed during the soft-start period. Any transition in the reference voltage after soft-start is complete occurs at the slew rate defined by the slowest soft-start time, or 0.067 mV/µs. For example, a trim which moves the reference by 10%, occurs in approximately 900 µs.

The default value of STEP_VREF_MARGIN_LOW is –30 (dec), corresponding to a default margin low voltage of –60 mV (–10%).

8.6.33 PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h)

The PCT_VOUT_FAULT_PG_LIMIT command is used to set the PGOOD, VOUT_UNDER_VOLTAGE (UV) and VOUT_OVER_VOLTAGE (OV) limits as a percentage of nominal.

The PCT_VOUT_FAULT_PG_LIMIT takes a one byte data word formatted as shown below:

The PGOOD, VOUT_UNDER_VOLTAGE (UV) and VOUT_OVER_VOLTAGE (OV) settings are shown in Table 9, as a percentage of nominal reference voltage on the FB pin.

The PGOOD pin may trip if the output voltage is too high (using PGH high) or too low (using PGL low). Additionally, the PGOOD pin has hysteresis.

Additionally, when output overvoltage (OV) is tripped, the output must lower below the PGH high threshold minus the hysteresis, before PGOOD and OV are reset. Likewise, when output undervoltage (UV) is tripped, the output must rise above the PGOOD high threshold plus the hysteresis, before PGOOD and UV are reset.

8.6.34 SEQUENCE_TON_TOFF_DELAY (MFR_SPECIFIC_08) (D8h)

The SEQUENCE_TON_TOFF_DELAY command is used to set the delay for turning on the device and turning off the device as a ratio of TON_RISE.

The SEQUENCE_TON_TOFF_DELAY takes a one byte data word formatted as shown below:

8.6.35 OPTIONS (MFR_SPECIFIC_21) (E5h)

The OPTIONS register can be used for setting user selectable options, as shown below.

The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command.

A “1” in any of these bit positions indicates that:

8.6.36 MASK_SMBALERT (MFR_SPECIFIC_23) (E7h)

The MASK SMBALERT command may be used to prevent a warning or fault condition from asserting SMBALERT.

8.6.37 DEVICE_CODE (MFR_SPECIFIC_44) (FCh)

The DEVICE_CODE command returns a two byte unsigned binary 12-bit device identifier code and 4-bit revision code in the following format.

This command provides similar information to the DEVICE_ID command but for devices that do not support block read and write functions.

The fixed, read-only values for each device are summarized below: