ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AGND | 32 | G | Ground pin, reference point for internal control circuitry. |
| BOOT | 26 | P | Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to PHASE pin. A high temperature (X7R) 0.1 μF or greater value ceramic capacitor is recommended. |
| CAT_FAULT# | 28 | O | Catastrophic Fault indicator, open-drain. The CAT_FAULT# indicator asserts low when any catastrophic fault event (over-voltage, under-voltage and over-temperature) happens. During nominal operation, the CAT_FAULT# indicator holds high. |
| DNC | 6 | — | Do Not Connect (DNC) pin. This pin is the output of internal circuitry and must be floating. Pin 6 and pin 37 can be shorted together but NO any other PCB connection is allowed on pin 6. |
| EN | 27 | I | Enable pin, an active-high input pin that, when asserted high, causes the converter to begin its soft-start sequence for its output voltage rail. When de-asserted low, the converter must de-assert VRRDY and begin the shutdown sequence of the output voltage rail and continue to completion. |
| GOSNS | 31 | I | Negative input of the differential remote sense circuit, connect to the ground sense point on the load side. |
| I2C_ADDR | 29 | I | The I2C address of the device is set by tying an external resistor between this pin and AGND. |
| I2C_SCL | 36 | I | I2C serial clock pin, open drain. |
| I2C_SDA | 1 | I/O | I2C bi-directional serial data pin, open drain. |
| NC | 37 | — | Not connected. This pin is floating internally. Pin 37 and pin 6 can be shorted together. |
| PGND | 7–10, 19 | G | Power ground for the internal power stage. |
| PHASE | 25 | — | Return for high-side MOSFET driver. Shorted to SW internally. Connect the bootstrap capacitor from BOOT pin to this pin. |
| PVIN | 20–24 | P | Power input for both the power stage. PVIN is the input of the internal VCC LDO as well. |
| SV_ALERT# | 35 | O | SVID active low ALERT# signal, open drain. This output is asserted to indicate the status of the converter has changed. |
| SV_CLK | 34 | I | SVID clock pin, open drain. |
| SV_DIO | 33 | I/O | SVID bi-directional data pin, open drain. |
| SW | 11–18 | O | Output switching terminal of the power converter. Connect these pins to the output inductor. |
| VCC/VDRV | 5 | P | Internal VCC LDO output and also the input for gate driver circuit. An external 5-V bias can be connected to this pin to save the power losses on the internal LDO. The voltage source on this pin powers both the internal control circuitry and the gate driver. A 2.2 μF (or 4.7 μF), at least 6.3 V rating ceramic capacitor is required to be placed from VCC/VDRV pin to PGND pins to decouple the noise generated by driver circuitry. Check layout guidelines for more details. |
| VINSENM | 4 | I | Negative input for the input power telemetry. Connect to the negative side of the input power sense resistor. Input voltage is also sensed at this pin. To minimize the impact from switching noise, a ceramic decoupling capacitor with at least 100 pF capacitance is required from this pin to PGND. Check layout guidelines for more details. |
| VINSENP | 3 | I | Positive input for the input power telemetry. Connect to the positive side of the input power sense resistor. To minimize the impact from switching noise, a ceramic decoupling capacitor with at least 100-pF capacitance is required from this pin to PGND. Check layout guidelines for more details. |
| VOSNS | 30 | I | Positive input of the differential remote sense circuit, connect to the Vout sense point on the load side. |
| VRRDY | 2 | O | Voltage regulator “Ready” output signal. The VRRDY indicator is asserted when the controller is ready to accept SVID commands after the EN is asserted. VRRDYalso de-asserts low when a shutdown fault occurs. This open-drain output requires an external pullup resistor. |