ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
CMD Address | ADh |
Write Transaction: | Write Byte |
Read Transaction: | Read Byte |
Format: | Unsigned Binary (1 byte) |
NVM Backup: | EEPROM |
Updates: | On-the-fly |
The COMP3 command contains 4 fields for configuring the control loop.
The EN_SS_DCM bit sets the operation mode during the soft-start ramp. With value "1" on this bit, the device is forced to under DCM operation during the soft-start ramp. This bit doesn't control the operation mode after the soft-start ramp completes.
The SEL_NOC_TON bit selects the on-time reference for a NOC operation and thus determines the high-side FET conduction time during a NOC operation period. The on-time option selected here can help to avoid two undesired behaviors:
These SEL_LO_CS bits select the LOUT (output inductor value) for the current sensing circuit. The TPS544C26 IC utilizes the output inductor value entered here to build an accurate output from the current sense circuit. Please choose a value closest to the inductor that is used in a BOM. For any inductor value higher than 400 nH, set SEL_LO_CS to 11b. Selecting a value that is significantly different from the real inductor (for example, 400 nH used but 100 nH selected) can lead to an inaccurate current sense output which can cause unexpected control loop behavior and also an inaccurate READ_IOUT telemetry report.
The DCLL bits determine the DC load line setting. Select a DCLL value per the requirement from the processor or the load, otherwise, the load regulation can be out of expectation.
Return to Supported I2C and Default Values.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reserved | EN_SS_DCM | SEL_NOC_TON | SEL_LO_CS | DCLL |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
7 | Reserved | R | 0b | Not used and always set to 0. |
6 | EN_SS_DCM | R/W | NVM |
0b: the operation during the soft-start ramp follows the configuration set by the FCCM bit in (A0h) SYS_CFG_USER1 register. 1b: Forced DCM operation during the soft-start ramp |
5 | SEL_NOC_TON | R/W | NVM | Select the on-time for NOC operation. See for more details |
4:3 | SEL_LO_CS | R/W | NVM | These bits select the
LOUT (output inductor value) for the current sensing
circuit. 00b: LOUT = 100 nH 01b: LOUT = 200 nH 10b: LOUT = 300 nH 11b: LOUT = 400 nH |
2:0 | DCLL | R/W | NVM | These bits determine the
DCLL setting. 000b: DCLL = 0 mΩ (VOUT maintains the regulation regardless of the load current) 001b: DCLL = 0.5 mΩ 010b: DCLL = 0.75 mΩ 011b: DCLL = 1.0 mΩ 100b: DCLL = 1.5 mΩ 101b: DCLL = 2.9 mΩ 110b: DCLL = 3.2 mΩ 111b: DCLL = 4.05 mΩ |
PROTOCOL_ID in (C2h) PROTOCOL_ID_SVID | SEL_NOC_TON | Option | tON_NOC (ns) |
---|---|---|---|
PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV) | 1 | Shorter tON_NOC | Use: Equation 9.
|
0 | Longer tON_NOC | Use: Equation 10.
|
|
PROTOCOL_ID = 00b or 11b (VOUT step = 10 mV) | 1 | Shorter tON_NOC | Use: Equation 11.
|
0 | Longer tON_NOC | Use: Equation 12.
|