For a synchronous buck converter, the inductor current increases at a linear rate determined by the input voltage, the output voltage, and the output inductor value during the high-side MOSFET on-time (ON time). During the low-side MOSFET on-time (OFF time), this inductor current decreases linearly per slew rate determined by the output voltage and the output inductor value. The inductor during the OFF time, even with a negative slew rate, usually flows from the device SW node to the load the device which is said to be sourcing current and the output current is declared to be positive. This section describes the overcurrent limit feature based on the positive low-side current. The next section describes the overcurrent limit feature based on the negative low-side current.

The positive overcurrent limit (OCL) feature in the TPS544C26 device is implemented to clamp low-side valley current on a cycle-by-cycle basis. The inductor current is monitored during the OFF time by sensing the current flowing through the low-side MOSFET. When the sensed low-side MOSFET current remains above the selected OCL threshold, the low-side MOSFET stays ON until the sensed current level becomes lower than the selected OCL threshold. This operation extends the OFF time and pushes the next ON time (where the high-side MOSFET turns on) out. As a result, the OCL bit in (7Bh) STATUS_IOUT is set, also the average output current sourced by the device is reduced. As long as the load pulls a heavy load where the sensed low-side valley current exceeds the selected OCL threshold, the device continuously operates in this clamping mode which extends the current OFF time and pushes the next ON time out. The device does not implement a fault response circuit directly tied to the overcurrent limit circuit, instead, the VOUT Tracking UVF function is utilized to shuts the device down under an overcurrent fault. During an overcurrent event, the current sunk by the load (I_OUT) exceeds the current sourced by the device to the output capacitors, thus, the output voltage tends to decrease. Eventually, when the output voltage falls below the selected undervoltage fault threshold, the VOUT Tracking UVF comparator detects and shuts down the device after the UVF Response Delay (programmable in (45h) VOUT_UV_FAULT_RESPONSE register). The device then responds to the Tracking UVF trigger per bit[3] RESTART selection in (45h) VOUT_UV_FAULT_RESPONSE register. With the RESTART bit unset (value "0"), the device latches OFF both high-side and low-side drivers. The latch is cleared with a reset of VCC or by toggling the EN pin. With the RESTART bit set (value "1"), the device enters hiccup mode and re-starts automatically after a hiccup sleep time of 56 ms, without limitation on the number of restart attempts. In other words, the response to an overcurrent fault is set by the programmed UVF response.

If an OCL condition happens during a soft-start ramp the device still operates with the cycle-by-cycle current limit based on the sensed low-side valley current. This operation can limit the energy charged into the output capacitors thus the output voltage likely ramps up slower than the desired soft-start slew rate. During the soft-start, the VOUT Tracking UVF comparator is disabled thus the device does not respond to a UVF event. Upon the completion of the soft-start, the VOUT Tracking UVF comparator is enabled, then the device starts responding to the UVF event.

The OCL feature in the device is implemented by detecting the low-side valley current through analog circuitries and has no relationship with the integrated Analog-to-Digital converter (ADC). The telemetry analog-front-end gets an input from the low-side current sense circuit and average low-side MOSFET current from the start to the end of each low-side MOSFET on time. By this method, the telemetry sub-system reports the load current (IOUT) which is the average value of the inductor current but not peak or valley values.