ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| CMD Address | 7Ch |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Backup: | No |
| Updates: | On-the-fly |
The STATUS_INPUT command returns one data byte with contents as follows. All supported bits can be cleared either by CLEAR_FAULTS, or individually by writing a "1" to the (7Ch) STATUS_INPUT register in their position. If a fault condition is still present when the corresponding bit is cleared, the fault bit is immediately set again.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R | R | R/W | R | R | R | R/W |
| PVIN_OVF | 0 | 0 | PVIN_UVF | 0 | 0 | 0 | PIN_OPW |
| LEGEND: R/W = Read/Write; R = Read only |
|
Bit |
Field |
Access |
Reset |
Description |
|---|---|---|---|---|
| 7 |
PVIN_OVF |
R/W |
0b |
0b: Latched flag indicating a PVIN OV fault has not occurred. 1b: Latched flag indicating a PVIN OV fault has occurred. |
| 6:5 | Not supported | R | 00b | Not supported and always set to 0. |
| 4 | PVIN_UVF | R/W | 0b |
0b: Latched flag indicating a PVIN UV fault has not occurred. 1b: Latched flag indicating a PVIN UV fault has occurred. |
| 3:1 | Not supported | R | 000b | Not supported and always set to 0. |
| 0 | PIN_ OPW | R/W | 0b |
0b: Latched flag indicating a PIN OP event has not occurred. 1b: Latched flag indicating a PIN OP event has occurred. |