TPS544C26 device has an internal 4.5-V LDO featuring input from PVIN and output to VCC/VDRV pin. When the PVIN voltage rises, the internal LDO is enabled automatically and starts regulating LDO output voltage on the VCC/VDRV pin. The VCC voltage provides the bias voltage for the internal analog circuitry in controller side and the VDRV voltage provides the supply voltage for the power stage side.

A 2.2-μF or 4.7-μF, at least 6.3-V rating ceramic capacitor must be closely placed from VCC/VDRV pin to PGND pin to decouple the noise generated by driver circuitry. Referring this decoupling capacitor to AGND introduces extra noise to the analog circuitry in controller, which likely causes more noise on digital interface pins.

An external bias ranging 4.75-V to 5.30-V can be connect to VCC/VDRV pin and power the IC. This enhances the efficiency of the solution because the VCC and VDRV power supply current now runs off this external bias instead of the internal linear regulator.

A VCC UVLO circuit monitors the VCC/VDRV pin voltage and disables the switching when VCC falls below the VCC UVLO falling threshold. Maintaining a stable and clean VCC/VDRV voltage is required for a smooth operation of the device.

Considerations when using an external bias on the VDRV and VCC pin are shown below:

• Connect the external bias to VCC/VDRV pin.
• When the external bias is applied on the VCC/VDRV pin earlier than PVIN rail, the internal LDO is be always forced off and the internal analog circuits have a stable power supply rail at their power enable.
• (Not recommended) When the external bias is applied on the VCC/VDRV pin late (for example, after PVIN rail ramp-up), any power-up and power-down sequencing can be applied as long as there is no excess current pulled out of the VCC/VDRV pin. Understand that an external discharge path on the VCC/VDRV pin, which can pull a current higher than the current limit of the internal LDO, can potentially turn off VCC LDO thereby shutting off the converter output.
• A good power-up sequence is: the external 5-V bias is applied first, then the 12 V bus is applied on PVIN, and then EN signal goes high.