ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| Register Address | A2h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Back-up: | EEPROM |
| Updates: | Update the I2C_ADDR value, set the OVRD_I2C_ADDR bit, Section 7.6.4 then VCC reset are all required for the device to respond to a new I2C address. |
The I2C_ADDR command reads the I2C device address when the address is determined by pin-strapping. When the OVRD_I2C_ADDR bit is set the device address is set by the value written into this register. Update the I2C_ADDR value, set the OVRD_I2C_ADDR bit, execute (15h) STORE_USER_ALL then VCC reset are all required for the device to respond to a new I2C address
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reserved | I2C_ADDR | ||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | Reserved | R | 0b | Reserved for TI usage. |
| 6:0 | I2C_ADDR | R/W | NVM | These bits set the I2C address. By default, the address is set through the resistor on the I2C_ADDR pin as described in Setting the I2C Address. The I2C address can be changed through these bits together using the OVRD_I2C_ADDR bit. The OVRD_I2C_ADDR bit must be set to "1", stored to NVM and the VCC resets before the TPS544C26 will respond to the programmed new address. |