ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| CMD Address | BBh |
| Write Transaction: | N/A |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
The STATUS2_SVID command contains direct copies of the bits of SVID (11h) STATUS_2 register. When a bit in the SVID (11h) STATUS_2 register is cleared via the SVID bus, the corresponding bit in I2C (BBh) STATUS2_SVID register also get cleared. There is no separate clear mechanism for the bits in BBh register via the I2C bus.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | R | R | R | R |
| Reserved | SVID_OCL_LATCH | SVID_frame_err | SVID_parity_err | ||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:3 | Reserved | R | 00000b | Not supported and always set to 0. |
| 2 | SVID_OCL_LATCH | R | Current status | Defined by Intel. Refer to Intel document for details. |
| 1 | SVID_frame_err | R | Current status | Defined by Intel. Refer to Intel document for details. |
| 0 | SVID_parity_err | R | Current status | Defined by Intel. Refer to Intel document for details. |