ZHCSR16 September 2022 TPS544C26
ADVANCE INFORMATION
| CMD Address | BAh |
| Write Transaction: | N/A |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
The STATUS1_SVID command contains direct copies of the bits of SVID (10h) STATUS_1 register. When a bit in the SVID (10h) STATUS_1 register is cleared via the SVID bus, the corresponding bit in I2C (BAh) STATUS1_SVID register also get cleared. There is no separate clear mechanism for the bits in BAh register via the I2C bus.
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | R | R | R | R |
| READ_STATUS2 | Reserved | VID_DAC_High | IccMaxAlert | ThermAlert | VR_Settled | ||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | READ_STATUS2 | R | Current status | Defined by Intel. Refer to Intel document for details. |
| 6:4 | Reserved | R | 000b | Not supported and always set to 0. |
| 3 | VID_DAC_High | R | Current status | Defined by Intel. Refer to Intel document for details. |
| 2 | IccMaxAlert | R | Current status | Defined by Intel. Refer to Intel document for details. |
| 1 | ThermAlert | R | Current status | Defined by Intel. Refer to Intel document for details. |
| 0 | VR_Settled | R | Current status | Defined by Intel. Refer to Intel document for details. |