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ZHCSB15B May 2013 – October 2023 TPS54531

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DDA|8
- MPDS092F

散热焊盘机械数据 (封装 | 引脚)

DDA|8
- PPTD058I

订购信息

8.2.2.11 Output Voltage Limitations

Because of the internal design of the TPS54531 device, any give voltage has both upper and lower output voltage limits for any given input voltage. The upper limit of the output-voltage set point is constrained by the maximum duty cycle of 91% and is calculated with Equation 20. The equation assumes the maximum ON resistance for the internal high-side FET.

Equation 20.

V_{O (M A X)} = 0.91 \times ((V_{I N (M I N)} - I_{O (M A X)} \times R_{D S (O N) M A X}) + V_{D}) - (I_{O (M A X)} \times R_{L}) - V_{D}

where

V_IN(MIN) = Minimum input voltage
I_O(MAX) = Maximum load current
V_D = Catch diode forward voltage
R_L = Output inductor series resistance

The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 21.

Equation 21.

V_{O (M I N)} = 0.089 \times ((V_{I N (M A X)} - I_{O (M I N)} \times R_{D S (O N) M I N}) + V_{D}) - (I_{O (M I N)} \times R_{L}) - V_{D}

where

V_IN(MAX) = Maximum input voltage
I_O(MIN) = Minimum load current
V_D = Catch diode forward voltage
R_L = Output inductor series resistance

This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device must be carefully checked to ensure proper functionality.