The VIN pin must be bypassed to ground with a low-ESR ceramic bypass capacitor. Care must be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the source of the anode of the catch diode. Figure 8-16 shows a PCB layout example. The GND pin must be tied to the PCB ground plane at the pin of the device. The PH pin must be routed to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, the catch diode and output inductor must be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the exposed thermal pad must be soldered directly to the top-side ground area under the device. Use thermal vias to connect the top-side ground area to an internal or bottom-layer ground plane. The total copper area must provide adequate heat dissipation. Additional vias adjacent to the device can be used to improve heat transfer to the internal or bottom-layer ground plane . The additional external components can be placed approximately as shown. Obtaining acceptable performance with alternate layout schemes can be possible, however this layout has been shown to produce good results and is intended as a guideline.