10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the A node of the catch diode. See Figure 57 for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad.

The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW connection is the switching node, the catch diode and output inductor should be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

10.2 Layout Example

Figure 57. PCB Layout Example

10.3 Power Dissipation

The following formulas show how to estimate the TPS54560-Q1 power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is operating in discontinuous conduction mode (DCM).

The power dissipation of the IC includes conduction loss (P_COND), switching loss (P_SW), gate drive loss (P_GD) and supply current (P_Q). Example calculations are shown with the 12 V typical input voltage of the design example.

Equation 50.

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Equation 51.

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Equation 52.

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Equation 53.

Where:

I_OUT is the output current (A).
R_DS(on) is the on-resistance of the high-side MOSFET (Ω).
V_OUT is the output voltage (V).
V_IN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW pin voltage rise time and can be estimated by trise = V_IN x 0.16 ns/V + 3 ns
Q_G is the total gate charge of the internal MOSFET
I_Q is the operating nonswitching supply current

Therefore,

Equation 54.

For given T_A,

Equation 55.

For given T_JMAX = 150°C

Equation 56.

Where:

Ptot is the total device power dissipation (W).
T_A is the ambient temperature (°C).
T_J is the junction temperature (°C).
R_TH is the thermal resistance of the package (°C/W).
T_JMAX is maximum junction temperature (°C).
T_AMAX is maximum ambient temperature (°C).

There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and PCB trace resistance impacting the overall efficiency of the regulator.

10.4 Safe Operating Area

The safe operating area (SOA) of the device is shown in Figure 58, through Figure 61 for 3.3 V, 5 V and 12 V outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at which the internal components are at or below the manufacturer’s maximum operating temperatures. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz. copper, similar to the EVM. Careful attention must be paid to the other components chosen for the design, especially the catch diode.

Figure 58. 3.3-V Outputs

Figure 60. 12-V Outputs

Figure 59. 5-V Outputs

Figure 61. Air Flow Conditions
V_IN = 36 V, V_O = 12 V