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6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Input voltage	VIN	–0.3	65	V
	EN	–0.3	8.4
	BOOT		73
	FB	–0.3	3
	COMP	–0.3	3
	RT/CLK	–0.3	3.6
Output voltage	BOOT-SW		8	V
	SW	–0.6	65
	SW, 10-ns Transient	–2	65
Operating junction temperature		–40	150	°C
Storage temperature range	T_STG	–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

		MIN	MAX	UNIT
V_ESD ⁽¹⁾	Human Body Model (HBM) ESD Stress Voltage ⁽²⁾		±2000	V
V_ESD ⁽¹⁾	Charged Device Model (HBM) ESD Stress Voltage ⁽³⁾		±500	V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. terminals listed as 1000V may actually have higher performance.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. terminals listed as 250V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Supply input voltage ⁽¹⁾	V_O + V_DO	60	V
V_O	Output voltage	0.8	58.8	V
I_O	Output current	0	5	A
T_J	Junction Temperature	–40	150	°C

(1) See Equation 1

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TPS54560B-Q1	UNIT
THERMAL METRIC⁽¹⁾⁽²⁾		DDA (8 PINS)	UNIT
θ_JA	Junction-to-ambient thermal resistance (standard board)	42.0	°C/W
ψ_JT	Junction-to-top characterization parameter	5.9	°C/W
ψ_JB	Junction-to-board characterization parameter	23.4	°C/W
θ_JCtop	Junction-to-case(top) thermal resistance	45.8	°C/W
θ_JCbot	Junction-to-case(bottom) thermal resistance	3.6	°C/W
θ_JB	Junction-to-board thermal resistance	23.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.

6.5 Electrical Characteristics

T_J = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN TERMINAL)
	Operating input voltage		4.5		60	V
	Internal undervoltage lockout threshold	Rising	4.1	4.3	4.48	V
	Internal undervoltage lockout threshold hysteresis			325		mV
	Shutdown supply current	EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V		2.25	4.5	μA
	Operating: nonswitching supply current	FB = 0.9 V, T_A = 25°C		146	175	μA
ENABLE AND UVLO (EN TERMINAL)
	Enable threshold voltage	No voltage hysteresis, rising and falling	1.1	1.2	1.3	V
	Input current	Enable threshold +50 mV		–4.6		μA
	Input current	Enable threshold –50 mV	–0.58	–1.2	-1.8	μA
	Hysteresis current		–2.2	–3.4	-4.5	μA
VOLTAGE REFERENCE
	Voltage reference		0.792	0.8	0.808	V
HIGH-SIDE MOSFET
	On-resistance	V_IN = 12 V, BOOT-SW = 6 V		92	190	mΩ
ERROR AMPLIFIER
	Input current			50		nA
	Error amplifier dc gain	V_FB = 0.8 V		10,000		V/V
	Min unity gain bandwidth			2500		kHz
	Error amplifier source/sink	V_(COMP) = 1 V, 100 mV overdrive		±30		μA
	COMP to SW current transconductance			17		A/V
CURRENT LIMIT
	Current limit test	All VIN and temperatures, Open Loop⁽¹⁾	6.3	7.9	9.5	A
		All temperatures, VIN = 12 V, Open Loop⁽¹⁾	6.3	7.9	9.5
		V_IN = 12 V, T_A = 25°C, Open Loop⁽¹⁾	7	7.9	8.8
THERMAL SHUTDOWN
	Thermal shutdown			176		°C
	Thermal shutdown hysteresis			12		°C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
	Switching frequency range using RT mode		100		2500	kHz
f_SW	Switching frequency	R_T = 200 kΩ	450	500	550	kHz
	Switching frequency range using CLK mode		160		2300	kHz
	RT/CLK high threshold			1.55	2	V
	RT/CLK low threshold		0.5	1.2		V

(1) Open Loop current limit measured directly at the SW terminal and is independent of the inductor value and slope compensation.

6.6 Timing Requirements

PARAMETER		TEST CONDITIONS	TYP	UNIT
ENABLE AND UVLO (EN TERMINAL)
	Enable to COMP active	V_IN = 12 V, T_A = 25°C	340	µs
INTERNAL SOFT-START TIME
	Soft-Start Time	f_SW= 500 kHz, 10% to 90%	2.1	ms
	Soft-Start Time	f_SW= 2.5 MHz, 10% to 90%	0.42	ms
ERROR AMPLIFIER
	Error amplifier transconductance (g_M)	–2 μA < I_COMP < 2 μA, V_COMP = 1 V	350	μs
	Error amplifier transconductance (g_M) during soft-start	–2 μA < I_COMP < 2 μA, V_COMP = 1 V, V_FB = 0.4 V	77	μs
CURRENT LIMIT
	Current limit threshold delay		60	ns
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
	Minimum CLK input pulse width		15	ns
	RT/CLK falling edge to SW rising edge delay	Measured at 500 kHz with RT resistor in series	55	ns
	PLL lock in time	Measured at 500 kHz	78	μs