The PWRGD pin is an open drain output. Once the FB pin is between 93% and 106% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 kΩ to a voltage source that is 5.5 V or less is recommended. A higher pull-up resistance reduces the amount of current drawn from the pull-up voltage source when the PWRGD pin is asserted low. A lower pull-up resistance reduces the switching noise seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but with reduced current sinking capability. The PWRGD will achieve full current sinking capability as VIN input voltage approaches 3 V.

The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal reference voltage. Also, PWRGD is pulled low, if UVLO or thermal shutdown are asserted or the EN pin pulled low.