The TPS54561 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW pins provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended for stable performance over temperature and voltage.

When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54561 will operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1V. When the voltage from BOOT to SW drops below 2.1 V, the high side MOSFET is turned off and an integrated low side MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high output voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.

Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode voltage and the printed circuit board resistance.

The start and stop voltage for a typical 5-V output application is shown in Figure 6-25 where the input voltage is plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within 1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where switching stops.

During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle PWM control.

At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 1 can be used to calculate the minimum input voltage for this condition.

Where:

• Dmax ≥ 0.9

• Vd = Forward Drop of the Catch Diode

• R_dc = DC resistance of output inductor

• R_DS(on) = 1 / (-0.3 × VB2SW² + 3.577 × VB2SW - 4.246)

• VB2SW = VBOOT + Vd

• VBOOT = (1.41 × V_VIN - 0.554 - Vd × fsw - 1.847 × 10³ × IB2SW) / (1.41 + fsw)

• fsw = Operating frequency in MHz

• IB2SW = 100 × 10^-6 A