ZHCSBY9G July 2013 – June 2021 TPS54561
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation Output Current
- 7.3.3 Pulse Skip Eco-mode
- 7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
- 7.3.5 Error Amplifier
- 7.3.6 Adjusting the Output Voltage
- 7.3.7 Enable and Adjusting Undervoltage Lockout
- 7.3.8 Soft Start/Tracking Pin (SS/TR)
- 7.3.9 Sequencing
- 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
- 7.3.11 Maximum Switching Frequency
- 7.3.12 Synchronization to RT/CLK Pin
- 7.3.13 Accurate Current Limit Operation
- 7.3.14 Power Good (PWRGD Pin)
- 7.3.15 Overvoltage Protection
- 7.3.16 Thermal Shutdown
- 7.3.17 Small Signal Model for Loop Response
- 7.3.18 Simple Small Signal Model for Peak Current Mode Control
- 7.3.19 Small Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Buck Converter for 7-V to 60-V Input to 5-V at 5-A Output
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design with WEBENCH® Tools
- 8.2.1.2.2 Selecting the Switching Frequency
- 8.2.1.2.3 Output Inductor Selection (LO)
- 8.2.1.2.4 Output Capacitor
- 8.2.1.2.5 Catch Diode
- 8.2.1.2.6 Input Capacitor
- 8.2.1.2.7 Slow Start Capacitor
- 8.2.1.2.8 Bootstrap Capacitor Selection
- 8.2.1.2.9 Undervoltage Lockout Set Point
- 8.2.1.2.10 Output Voltage and Feedback Resistors Selection
- 8.2.1.2.11 Compensation
- 8.2.1.2.12 Power Dissipation Estimate
- 8.2.1.2.13 Safe Operating Area
- 8.2.1.2.14 Discontinuous Conduction Mode and Eco-mode Boundary
- 8.2.1.3 Application Curves
- 8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output
- 8.2.3 Split-Rail Topology for Positive Input to Negative and Positive Output
- 8.2.1
Buck Converter for 7-V to 60-V Input to 5-V at 5-A Output
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.13 Accurate Current Limit Operation
The TPS54561 implements peak current mode control in which the COMP pin voltage controls the peak current of the high side MOSFET. A signal proportional to the high side switch current and the COMP pin voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the peak switch current limit. The TPS54561 provides an accurate current limit threshold with a typical current limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current. The relationship between the inductor value and the peak inductor current is shown in Figure 7-16.
Figure 7-16 Current Limit Delay