8.3.11 Power-Good (PWRGD)

The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10% below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold or SS/ENA is low, or a thermal shutdown occurs. When VIN ≥ UVLO threshold, SS/ENA ≥ enable threshold, and VSENSE > 90% of V_ref, the open drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of V_ref and a 35-μs falling edge deglitch circuit prevent tripping of the power good comparator due to high frequency noise.