ZHCSLU7A September 2020 – August 2021 TPS54618C-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation and Output Current
- 7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
- 7.3.4 Error Amplifier
- 7.3.5 Voltage Reference
- 7.3.6 Adjusting the Output Voltage
- 7.3.7 Enable and Adjusting Undervoltage Lockout
- 7.3.8 Soft-Start Pin
- 7.3.9 Sequencing
- 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.11 Overcurrent Protection
- 7.3.12 Frequency Shift
- 7.3.13 Reverse Overcurrent Protection
- 7.3.14 Synchronize Using the RT/CLK Pin
- 7.3.15 Power Good (PWRGD Pin)
- 7.3.16 Overvoltage Transient Protection
- 7.3.17 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Step One: Select the Switching Frequency
- 8.2.2.2 Step Two: Select the Output Inductor
- 8.2.2.3 Step Three: Choose the Output Capacitor
- 8.2.2.4 Step Four: Select the Input Capacitor
- 8.2.2.5 Step Five: Choose the Soft-Start Capacitor
- 8.2.2.6 Step Six: Select the Bootstrap Capacitor
- 8.2.2.7 Step Eight: Select Output Voltage and Feedback Resistors
- 8.2.2.8 Step Nine: Select Loop Compensation Components
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
8.2.2.8 Step Nine: Select Loop Compensation Components
There are several industry techniques used to compensate DC–DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54618C-Q1. Because the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use SwitcherPro™ software for a more accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1, must be calculated using Equation 36 and Equation 37. For COUT, the derated capacitance value is 82.5 µF. Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency, fc. For the example design, fpmod is 6.43 kHz and fzmod is 643 kHz. Equation 38 is the geometric mean of the modulator pole and the esr zero and Equation 39 is the mean of modulator pole and the switching frequency. Equation 38 yields 64.3 kHz and Equation 39 gives 56.7 kHz. The lower value of Equation 38 or Equation 39 is the maximum recommended crossover frequency. For this example, a lower fc value of 40 kHz is specified. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
The compensation design takes the following steps:
- Set up the anticipated crossover frequency. Use Equation 40 to calculate the resistor value of the compensation network. In this example, the anticipated crossover frequency (fc) is 40 kHz. The power stage gain (gmps) is 25 A/V and the error amplifier gain (gmea) is 245 μA/V.
Equation 40.
- Place compensation zero at the pole formed by the load resistor and the output capacitor. The capacitor of the compensation network can be calculated from Equation 41.
Equation 41.
- An additional pole can be added to attenuate high-frequency noise. In this application, it is not necessary to add it.
From the previously listed procedures, the compensation network includes a 7.50-kΩ resistor and a
3300-pF capacitor.