Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance.
- Minimize the loop area formed by the bypass
capacitor connections and the VIN pins. See Figure 10-1 for a PCB layout example.
- The GND pins and AGND pin should be tied directly
to the power pad under the TPS54618C-Q1 device. The power pad must
be connected to any internal PCB ground planes using multiple vias directly
under the device. Additional vias can be used to connect the top-side ground
area to the internal planes near the input and output capacitors. For operation
at full rated load, the top-side ground area along with any additional internal
ground planes must provide adequate heat dissipating area.
- Place the input bypass capacitor as close to the device as possible.
- Route the PH pin to the output inductor. Because the PH connection is the switching node, place the output inductor close to the PH pins. Minimize the area of the PCB conductor to prevent excessive capacitive coupling.
- The boot capacitor must also be located close to the device.
- The sensitive analog ground connections for the
feedback voltage divider, compensation components, soft-start capacitor, and
frequency set resistor must be connected to a separate analog ground trace as
shown in Figure 10-1.
- The RT/CLK pin is particularly sensitive to noise
so the RT resistor must be located as close as possible to the device and routed
with minimal trace lengths.
- The additional external components can be placed
approximately as shown. It is possible to obtain acceptable performance with
alternate PCB layouts, however, this layout has been shown to produce good
results and can be used as a guide.