An internal phase locked loop (PLL) has been implemented to allow synchronization from 200 kHz to 1600 kHz, and to easily switch from RT mode to CLK mode.

To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle from 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin.

In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 7-9. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. TI does not recommended switching from the CLK mode back to the RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by RT resistor.

Figure 7-9 Works With Both RT Mode and CLK Mode