The PWRGD pin is an open-drain output. Once the VSENSE pin is between 94% and 104% of the internal voltage reference the PWRGD pin pulldown is deasserted and the pin floats. TI recommends using a pullup resistor from the values of 10 kΩ to 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1 V but with reduced current sinking capability. The PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5 V.

The PWRGD pin is pulled low when VSENSE is lower than 92% or greater than 106% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN pin is pulled low or the SS/TR pin is below 1.4 V.