7.3.14 Power Good (PWRGD Pin)

The PWRGD pin is an open-drain output and pulls the PWRGD pin low when the VSENSE voltage is less than 91% or greater than 105% of the nominal internal reference voltage.

There is a 2% hysteresis, so once the VSENSE pin is within 93% to 103% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. TI recommends to use a pullup resistor between the values of
1 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.2 V.