SLVSH95 July 2024 TPS546C25
ADVANCE INFORMATION
The internal compensation of the device covers a wide range of applications. Some settings are adjusted automatically, such as the zero frequency of the error amplifier, which is adjusted with frequency selection. Other settings are determined by pin-strapping selection of MSEL2 or setting through PMBus.
FB_ZERO_TAU is the setting for the error amplifier zero setting:
The RAMP sets the internal inner-loop RAMP amplitude. See Programming MSEL2 and COMP for a full description of the RAMP settings available through pinstrapping and PMBus. Start with the 120mv setting. This selection must give the best compromise between jitter and transient response. A larger RAMP can improve jitter at the expense of lower phase margin, necessitating the need for a feed-forward capacitor (across an upper voltage setting divider resistor).
When using the internal divider to set the output voltage, GAIN is used to make sure the feedback loop has enough loop gain to provide stability and good load transient performance. Select the GAIN setting according to the VOUT_SCALE_LOOP parameter setting.
Gain | VOSL |
---|---|
3 | 0.125 |
10 | 0.25 |
15 | 0.5 |
30 | 1 |
For converters with external voltage setting resistors, begin with the GAIN setting as in C above, and divide by the voltage setting resistor ratio.
The device uses D-CAP4 control to achieve a fast load transient response while maintaining ease-of-use. The D-CAP4 control architecture includes an internal ripple generation network enabling the use of very low ESR output capacitors such as multi-layered ceramic capacitors (MLCC) and low ESR polymer capacitors. No external current sensing network or voltage compensators are required with D-CAP4 control architecture.
The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine with the voltage feedback signal to regulate the loop operation. D-CAP4 control architecture reduces loop gain variation across VOUT, enabling a fast load transient response across the entire output voltage range with one ramp setting. The R-C time-constant of the internal ramp circuit sets the zero frequency of the ramp, similar to other R-C based internal ramp generation architectures. The reduced variation in loop gain also mitigates the need for a feedforward capacitor to optimize the transient response. The ramp amplitude varies with VIN to minimize variation in loop gain across input voltage, commonly referred to as input voltage feedforward.
The device uses internal circuitry to correct for the DC offset caused by the injected ramp, and significantly reduces the DC offset caused by the output ripple voltage, especially with light load current. For any control topologies supporting no external compensation, there is a minimum range, maximum range, or both, for the output filter to support. The output filter used for a typical buck converter is a low-pass L-C circuit. This L-C filter has double pole. At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per decade and increases the phase by 90 degrees per decade above the zero frequency.
The inductor and capacitor selected for the output filter must be such that the double pole is located no higher than 1/30th of the steady-state operating frequency.
The compensation and output filter must be considered together. Choosing very small output capacitance leads to a high frequency L-C double pole which causes the overall loop gain to stay high until the L-C double frequency. Given the zero from the internal ripple generation network is a relatively high frequency as well, the loop with very small output capacitance can have too high of a crossover frequency which can cause instability.
In general, where reasonable (or smaller) output capacitance is desired, output ripple requirement and load transient requirement can be used to determine the necessary output capacitance for stable operation. For the maximum output capacitance recommendation, select the inductor and capacitor values so that the L-C double pole frequency is no less than 1/100th of the operating frequency. With this starting point, verify the small signal response on the board using the following criteria: The phase margin at the loop crossover is greater than 50 degrees. The actual maximum output capacitance can go higher as long as phase margin is greater than 50 degrees. However, small signal measurement (Bode plot) must be done to confirm the design.
If MLCCs are used, consider the derating characteristics to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10µF, X5R and 6.3V, the derating by DC bias and AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case is 40% and 4µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in the application.
For large output filters with an L-C double pole near 1/100th of the operating frequency, additional phase boost can be required. A feedforward capacitor placed in parallel with RFB_HS can boost the phase. Refer to the Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor application report for details. Besides boosting the phase, a feedforward capacitor feeds more VOUT node information into the FB node through AC coupling. This feedforward during load transient event enables faster response of the control loop to a VOUT deviation. However, this feedforward during steady state operation also feeds more VOUT ripple and noise into FB. High ripple and noise on FB usually leads to more jitter, or even double-pulse behavior. To determine the final feedforward capacitor value impacts to phase margin, load transient performance, ripple, and noise on FB must all be considered.