When an external bias that is at a different level from the main V_IN bus is applied to the VCC/VDRV pin, the device can be configured to split rail by using both the main V_IN bus and the VCC bias. Connecting a valid bias rail to the VCC/VDRV pin overrides the internal VCC LDO, saving power loss on that linear regulator. This configuration helps improve overall system-level efficiency but requires a valid VCC bias. A 5.0V rail is the common choice for VCC bias. With a stable VCC bias, the V_IN input range under this configuration can be as low as 2.7V and up to 18V.

The noise of the external bias affects the internal analog circuitry. To make sure of a proper operation, a clean, low-noise external bias, and a local decoupling capacitor from the VCC pin to PGND pin are required. Figure 6-6 shows an example for this split rail configuration.

The VCC external bias current during nominal operation varies with the bias voltage level and the switching frequency. For example, by setting the device to skip mode, the VCC pin draws less and less current from the external bias when the switching frequency decreases under light load conditions. The typical VCC external bias current under FCCM operation is listed in the Electrical Characteristics table to help the user prepare the capacity of the external bias.

Under split rail configuration, PVIN, VCC bias, and CTRL are the signals to enable the part. For the start-up sequence, TI recommends that the external bias is applied on the VCC/VDRV pin earlier than PVIN rail. A practical start-up sequence example is the external 5V bias is applied first, then the 12V bus is applied on PVIN, and then CTRL signal goes high.

Figure 6-6 Split Rail Configuration With External VCC Bias