The device uses D-CAP4 control to achieve a fast load transient response while maintaining ease-of-use. The D-CAP4 control architecture includes an internal ripple generation network enabling the use of very lowESR output capacitors such as multi-layered ceramic capacitors (MLCC) and low ESR polymer capacitors. No external current sensing, ripple injection or voltage compensation networks are required with D-CAP4 control architecture. The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine with the voltage feedback signal to regulate the loop operation, allowing the use of ultra-low ESR polymer and multi-layer ceramic capacitors (MLCCs).

D-CAP4 control architecture reduces loop gain variation across VOUT, enabling a fast load transient response across the entire output voltage range with one ramp setting. Unlike earlier D-CAP2 and D-CAP3 architectures, D-CAP4 uses a fixed ramp amplitude each switching cycle and a forward GAIN path to improve transient response and pulse frequency jitter while an error integrator provides high DC set-point accuracy.

The Ramp amplitude per switching cycle is

Due to the limited number of pin-programmable Ramp and GAIN options, and the dependance of the control loop performance on the output inductor, TI recommends that designs using pin programming compensation consider the available loop options when selecting the inductor and the minimum and maximum capacitance that the compensation options support when selecting the capacitor.

When using PMBus programmed compensation through (D4h) COMP, the range and resolution of available Ramp voltages and GAIN options is generally broad enough that designs can follow a more traditional design flow where the inductor is selected based on switching frequency and ripple current, and then capacitors are selected to meet ripple and transient requirements, then finally Ramp and GAIN is selected to make sure of stability with the inductor and capacitor, however many designers can find following the Compensation First design flow to narrow the choice of inductors easier, and then selecting a more optimized Ramp / GAIN option after the inductor has been selected.

Compensation First Design Procedure

Evaluate the maximum inductor value, which can be used with each compensation option while still meeting the application transient requirements. To do this action, calculate the maximum dynamic output impedance needed to meet the transient requirements for the application.

For each of the six pin programmable V_ramp / GAIN options, calculate the maximum inductance that can be used with that ramp to achieve the required output impedance

With the maximum inductor value, estimate the peak to peak inductor ripple current for each available V_ramp / GAIN compensation option and select an inductor whose peak to peak ripple current is between 10% and 40% of the expected full load current.

Selecting an inductor close to the maximum inductor meeting the dynamic impedance requirements minimizes over design and reduces the minimum amount of capacitance required to maintain stability while picking a smaller inductor reduces the amount of capacitance required to meet large-signal overshoot requirements, especially at low input voltages.

After an inductor has been selected, calculate the closed loop, mid-band dynamic output impedance by arranging the maximum inductance equation

To estimate the linear transient performance

The minimum capacitance for stability is

The minimum capacitance to meet large signal overshoot is

The maximum recommended capacitance places the L-C resonant frequency no less than ½ the integrator zero frequency, which can be estimated by