SLVSH95 July 2024 TPS546C25
ADVANCE INFORMATION
The device provides four IC pins that allow the initial PMBus programming value on critical PMBus commands to be selected by the resistors connected to that pin without requiring PMBus communication. Whether a specific PMBus command is initialized to the value selected by the detected resistance or stored NVM memory is determined by the commands bit in the PIN_DETECT_OVERRIDE Command.
| Function | Pin Used for Pinstrap | Pin Strap Order |
|---|---|---|
|
Primary / Secondary Internal or external feedback divider Overcurrent Limit (OCL) Soft start Fault response |
MSEL1 | 1 |
|
Primary: Phase quantity Mode (FCCM/DCM) Primary (Common) PMBus address |
PMB_ADDR | 2 |
|
Secondary: Phase location Unique PMBus address |
||
|
Primary: Switching frequency (FSW) RAMP GAIN |
MSEL2 | 3 |
|
Switching Frequency (FSW) Overcurrent Limit (OCL) |
||
|
Primary when internal feedback divider is used: VOUT VOSL NRSA VOUT_MAX VOUT_MIN Note: Pinstrap is not used when external feedback divider is selected with MSEL1, and the pin becomes FB |
VSEL/FB | 4 |
|
Secondary does not use this pinstrap |
The high precision Pin-Detection programming can be sensitive to PCB contamination from flux, moisture, and debris. As such, users must consider committing Pin Programmed values to User Non-Volatile memory and disable future use of Pin Strapped values as part of the product flow. The programming sequence to commit Pin Programmed PMBus register values to NVM and disable future use of Pin Strapped programming is: