Only the loop controller device (U1) uses the resistor to AGND for MSEL1 to program the (B1h) USER_DATA_01 (COMPENSATION_CONFIG) values to set the following voltage loop and current loop gains. The MSEL1 pin of loop follower devices are not used. For options other than the EEPROM code (MSEL1 shorted to AGND or MSEL1 to AGND resistor code 0) the current and voltage loop zero and pole frequencies are scaled with the programmed switching frequency.

Calculate the mid-band current loop gain with Equation 26. The resulting value is 3.3. Find the smaller value closest in the look-up table Table 7-9 and this is 3.

To calculate the target voltage loop gain, first use Equation 27 through Equation 29 to calculate the output impedance. Use Equation 30 to calculate the target voltage loop gain. With an estimated 85% derating, the ceramic capacitor impedance is 2.4 mΩ. The bulk capacitor impedance is 2.9 mΩ. The total output impedance is 1.3 mΩ. When using a stacked configuration, the CSA gain must be divided by the number of phases when calculating the target voltage loop gain. The resulting target voltage loop gain is 4.7. Find the smaller value closest in the look-up Table 7-9 for voltage loop gain and this is 4.

These settings gives a stable design but through bench evaluation the voltage loop gain was reduced to 2 to improve the gain and phase margin. The current loop and voltage loop gains are selected with compensation setting 8. With (33h) FREQUENCY_SWITCH of 550 kHz, this compensation setting can be selected using a single resistor to AGND. A 5.62-kΩ resistor to AGND at MSEL1 programs the desired settings.