ZHCSQY3 march 2023 TPS546D24S
PRODUCTION DATA
| CMD Address | 45h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| Phased: | No |
| NVM Back-up: | EEPROM |
| Updates: | On-the-fly |
The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in response to an output undervoltage fault. Upon triggering the overvoltage fault, the TPS546D24S responds according to the data byte below, and the following actions are taken:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| VO_UV_RESP | VO_UV_RETRY | VO_UV_DLY | |||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:6 | VO_ UV_ RESP | RW | NVM | Output undervoltage response 00b: Ignore. Continue operating without interruption. 01b: Shutdown after Delay, as set by VO_UV_DELY 10b: Shutdown Immediately Other: Invalid/Unsupported |
| 5:3 | VO_ UV_ RETRY | RW | NVM | Output undervoltage retry 0d: Do not attempt to restart (latch off). 1d-6d: After shutting down, wait one HICCUP period, and attempt to restart upto 1 - 6 times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off). 7d: After shutting down, wait one HICCUP period, and attempt to restart indefinitely, until commanded OFF, or a successful start-up occurs. |
| 2:0 | VO_ UV_ DLY | RW | NVM | Output undervoltage delay time for respond after delay and HICCUP 0d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE 1d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE 2d - 4d: Shutdown delay of three PWM_CLK, HICCUP equal to 2 - 4 times TON_RISE 5d - 7d: Shutdown delay of seven PWM_CLK, HICCUP equal to 5 - 7 times TON_RISE |
Attempts to write (45h) VOUT_UV_FAULT_RESPONSE to any value outside those specified as valid will be considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.