10.1 Layout Guidelines

Before beginning a design using the TPS548A20 , consider the following:

• Place the power components (including input and output capacitors, the inductor, and the TPS548A20 ) on the solder side of the PCB. In order to shield and isolate the small signal traces from noisy power lines, insert and connect at least one inner plane to ground.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and ADDR must be placed away from high-voltage switching nodes such as SW and VBST to avoid coupling. Use internal layers as ground planes and shield the feedback trace from power traces and components.
• Pin 22 (GND pin) must be connected directly to the thermal pad. Connect the thermal pad to the PGND pins and then to the GND plane.
• Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC-current loop.
• Place the feedback resistor near the IC to minimize the VFB trace distance.
• Place the frequency-setting resistor (ADDR), OCP-setting resistor (R_TRIP) and mode-setting resistor (R_MODE) close to the device. Use the common GND via to connect the resistors to the GND plane if applicable.
• Place the VDD and VREG decoupling capacitors as close to the device as possible. Provide GND vias for each decoupling capacitor and ensure the loop is as small as possible.
• The PCB trace is defined as switch node, which connects the SW pins and high-voltage side of the inductor. The switch node should be as short and wide as possible.
• Use separated vias or trace to connect SW node to the snubber, bootstrap capacitor, and ripple-injection resistor. Do not combine these connections.
• Place one more small capacitor (2.2 nF, 0402 size) between the VIN and PGND pins. This capacitor must be placed as close to the IC as possible.
• TI recommends placing a snubber between the SW shape and GND shape for effective ringing reduction. The value of snubber design starts at 3 Ω + 470 pF.
• Consider R-C-C_C network (Ripple injection network) component placement and place the AC coupling capacitor, C_C, close to the device, and R and C close to the power stage.
• See Figure 50 for the layout recommendation.

10.2 Layout Example

Figure 50. Layout Recommendation