Before beginning a design using the device,
consider the following:
- Place the power components (including input and
output capacitors, the inductor, and the IC) on the
top side of the PCB. To shield and isolate the small
signal traces from noisy power lines, insert at
least one solid ground inner plane.
- VIN decoupling capacitors are
important for FET robustness. A 1-μF/25-V/X6S/0402 ceramic capacitor on VIN
pin 21 is required. The PGND vias for this decoupling capacitor must be
placed so that the decoupling capacitor is closer to IC than the PGND vias.
To lower ESL from via connection, two 8-mil vias are recommended for the
PGND connection to inner PGND plane.
- A 1-μF/25-V/X6S/0402 ceramic
capacitor on VIN pin 10 is highly recommended. If this 0402 size capacitor
is not used, the bigger size VIN decoupling capacitors (0603 or 0805 size)
are required to be placed as close as possible to IC pin 10 and pin 11.
- Two 1-μF/25-V/X6S/0402 ceramic capacitors on the
bottom layer are recommended for high current
applications (Iout > 13 A). One of these two
capacitors must be centered between VIN pin 10 and
pin 21. To have good connection for this capacitor,
a VIN copper on bottom layer and two VIN vias are
needed. The other one can be placed close to IC
package just like a mirrored copy to the 0402
capacitor on top layer.
- At least six PGND vias are
required to be placed as close as possible to the PGND pins (pin 11 to pin
15). This minimizes parasitic impedance and also lowers thermal
resistance.
- Place the VCC decoupling
capacitor (2.2-μF/6.3-V/X6S/0402 or 2.2-μF/6.3-V/X7R/0603) as close as
possible to the device. Ensure the VCC decoupling loop is smallest.
- Place BOOT capacitor as close
as possible to the BOOT and SW pins. Use traces with a width of 12 mil or
wider to route the connection. TI recommends using a 0.1-µF to 1-µF
bootstrap capacitor with 10-V rating.
- The PCB trace, which connects
the SW pin and high-voltage side of the inductor, is defined as switch node.
The switch node must be as short and wide as possible.
- Always place the feedback
resistors near the device to minimize the FB trace distance, no matter
single-end sensing or remote sensing.
- For remote sensing, the connections from the FB
voltage divider resistors to the remote location
must be a pair of PCB traces with at least 12-mil
trace width, and must implement Kelvin sensing
across a high bypass capacitor of 0.1 μF or
higher. The ground connection of the remote
sensing signal must be connected to VSNS– pin. The
VOUT connection of the remote sensing
signal must be connected to the feedback resistor
divider with the lower feedback resistor
terminated at VSNS– pin. To maintain stable output
voltage and minimize the ripple, the pair of
remote sensing lines must stay away from any noise
sources such as inductor and SW nodes, or high
frequency clock lines. TI recommends to shield the
pair of remote sensing lines with ground planes
above and below.
- For single-end
sensing, connect the higher FB resistor to a high-frequency local
bypass capacitor of 0.1 μF or higher, and short VSNS– to AGND with
shortest trace.
- This device does not require a capacitor from
SS/REFIN pin to AGND, thus TI does not recommend to
place a capacitor from SS/REFIN pin to AGND. If both
CSS/REFIN-to-VSNS– and
CSS/REFIN-to-AGND capacitors exist,
place CSS/REFIN-to-VSNS– more closely
with shortest trace to VSNS– pin.
- Pin 2 (AGND pin) must be
connected to a solid PGND plane on inner layer. Use the common AGND via to
connect the resistors to the inner ground plane if applicable.
- See Section 8.4.2 for the layout recommendation.