The SW pins connect to the switching node of the power conversion stage. The SW pins act as the return path for the high-side gate driver. During nominal operation, the voltage swing on SW normally traverses from below ground to above the input voltage. Parasitic inductance in the PVIN to PGND loop (including the component from the PCB layout and also the component inside the package) and the output capacitance (COSS) of both power FETs form a resonant circuit that can produce high frequency (> 100 MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. TPS548C26 high-side gate driver is fine tuned to minimize the peak ringing amplitude so that a RC snubber on SW node is usually not needed. However, TI highly recommends for the user to measure the voltage stress across either the high-side or low-side FET and ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit listed in the Absolute Maximum Ratings table.