When an external bias that is at a different level from the main V_IN bus, is applied to the VDRV pin, the device can be configured to split rail by using both the main V_IN bus and the VDRV bias. Connecting a valid bias rail to the VDRV pin overrides the internal VCC LDO, saving power loss on that linear regulator. This configuration helps improve overall system-level efficiency but requires a valid VCC bias. A 5.0-V rail is the common choice for the VDRV bias. With a stable VDRV bias, the V_IN input range under this configuration can be as low as 2.7 V and up to 16 V.

The noise of the external bias affects the internal analog circuitry. To ensure a proper operation, a clean, low-noise external bias, and a local decoupling capacitor from the VDRV pin to PGND pin are required. Figure 7-2 shows an example for this split rail configuration.

The VDRV external bias current during nominal operation varies with the bias voltage level and the switching frequency. For example, by setting the device to skip mode, the VDRV pin draws less and less current from the external bias when the switching frequency decreases under light load condition. The typical VDRV external bias current under FCCM operation is listed in the Electrical Characteristics table to help the user prepare the capacity of the external bias.

Under split rail configuration, PVIN, VDRV bias, and EN are the signals to enable the part. For the start-up sequence, it is recommended that the external bias is applied on the VDRV pin earlier than PVIN rail. A practical start-up sequence example is the external 5-V bias is applied first, then the 12-V bus is applied on PVIN, and then EN signal goes high.

Figure 7-2 Split Rail Configuration with External VCC Bias