7.3.1 Frequency Selection

The oscillator frequency of this converter can be selected to be one of three options: 4, 7, or 10 MHz. The per phase switching frequency of the converter is half the oscillator frequency (that is, 2, 3.5, or 5 MHz per phase). The internal oscillator frequency is selected by programming the SS/FSEL pin. The resistor programming information is shown in Table 1. The frequency setting is latched in at power up and cannot be changed during operation. Cycling the input power or the EN pin will reset the frequency setting.

7.3.2 External Clock Syncronization

An external clock can be connected to the SYNC pin. The external clock signal overrides the internal oscillator and is used as the system clock. This feature enables the user to synchronize the switching events to a master clock on their board and reduce/manage the ripple on the input capacitors. The internal phase locked loop (PLL) has been implemented to allow synchronization at frequencies between ±10% of the nominal oscillator frequency programmed on the SS/FSEL pin. This allows the user to easily switch from the internal oscillator mode to the external clock mode. Before the external clock is present or after it is removed, the device with default to the internal oscillator setting as programmed on the SS/FSEL pin.

To implement the synchronization feature, connect a square wave clock signal to the SYNC pin with a duty cycle between 20% and 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the rising edge of the SYNC pin. The device can be configured for operation in applications where both an internal oscillator mode and an external synchronization clock mode are needed. Before the external clock is present, the device functions with the internal oscillator and the switching frequency is set by the R_SS/FSEL resistor. When the external clock is present, the SYNC mode overrides the internal oscillator. The first time the SYNC pin is pulled above the SYNC high threshold (2 V), the device switches from the internal oscillator mode to the SYNC mode and the PLL starts to lock onto the frequency of the external clock. When the external SYNC clock is removed, the converter will transition back to the internal oscillator after 4 internal clock cycles.

7.3.3 Adjusting the Output Voltage

The output voltage is set by connecting a resistor divider network from the output voltage to the FB pin of the device and to AGND. It is recommended that the lower divider resistor maintain a range between 1 kΩ and 10 kΩ. To change the output voltage of a design, it is necessary to select the value of the upper resistor. Equation 2 can be used to select the upper resistor. Selecting the value of the upper resistor can change the output voltage between 0.508 V and 2 V. The minimum output setpoint voltage cannot be less than the reference voltage of 0.508 V. The maximum output voltage can be limited by minimum input voltage as shown in Figure 24. The recommended minimum input voltage should be at least five times the output voltage as shown in Figure 25. This is due to the nature of the series capacitor buck converter.

7.3.4 Soft Start

Soft start is an important feature that limits current inrush into the converter and reduces the load on the bus converter that supplies this device. During soft start, the internal reference voltage is slowly ramped up to the nominal internal reference voltage (~0.5 V). This slowly increases the commanded output voltage of the converter and reduces the initial surge in current. PGOOD remains low during soft start, the PLL is not active, and output UVP/OVP faults are disabled. After the soft start interval is complete, the converter operates with normal operating conditions and PGOOD will no longer be held low when the output is within bounds.

Soft-start time is programmed with an external resistor on SS/FSEL pin (or by shorting to ground or by leaving the pin open). There are multiple soft-start time options per operating frequency available to the user through the SS/FSEL pin. The soft-start setting is latched in at power up or when the EN pin voltage is set high. Resistors used for programing the SS/FSEL pin must have ±1% or lower tolerance. The following frequencies and soft start times can be programmed on the SS/FSEL pin.

7.3.5 Startup into Pre-biased Outputs

The device prevents the low-side MOSFETs from discharging a pre-biased output. During pre-biased startup, the low-side MOSFETs do not turn on until after the phase A high-side MOSFET has started switching. The high-side MOSFETs do not start switching until the internal soft-start reference voltage exceeds the voltage at the FB pin. It is required to first apply the gate driver supply voltage (VG+) before starting up into pre-biased loads. Alternatively, 6.8 µF bypass capacitance or more can be used.

7.3.6 Power Good (PGOOD)

The Power Good (PGOOD) pin is an open drain output. After startup when the FB pin is typically between 95% and 105% of the internal voltage reference, the PGOOD pin pull-down is de-asserted and the pin floats. It is recommended to use a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PGOOD is in a defined state once the VIN input voltage is greater than approximately 1.2 V but with reduced current sinking capability. The PGOOD achieves full current sinking capability once the VIN input voltage is above the input UVLO. The PGOOD pin is pulled low when the FB pin voltage is typically lower than 95% or greater than 105% of the nominal internal reference voltage. A resistor-capacitor (RC) filter can be connected to the PGOOD pin to filter out PGOOD being pulled low during large load transients if low output capacitance is used. The PGOOD pin is also pulled low if a fault is detected, the EN pin is pulled low, or the converter is performing its soft-start power up sequence.

7.3.7 Overcurrent Protection

The device protects itself from an overcurrent condition by a current limit detector. The device senses inductor currents using the low side MOSFETs. After three sequential overcurrent measurements are made (in phase A or B), the over current flag is triggered, the converter switches are turned off, and PGOOD is pulled low. The converter attempts to restart after a hiccup interval counter has expired (that is, 32.8 ms, 18.7 ms, or 13.1 ms when in 4 MHz, 7 MHz, or 10 MHz mode, respectively). This provides a hiccup response to an overcurrent condition.

The two overcurrent trip points are based on two full load applications of 7.5 A or 10 A. The overcurrent trip points correspond to the load demanding 1.5 times the full load current (11.25 A and 15 A, respectively). This provides enough margin for brief overshoots in inductor currents during a load transient while at the same time protecting against short circuits or other potentially catastrophic faults on the output. The table below lists the resistor values for programming the ILIM pin to select the desired overcurrent limit. Programming resistors with up to ±5% variation can be used. The current limit selection is latched in at power up and cannot be changed without cycling power input or the EN pin voltage.

7.3.8 Light Load Operation

The converter operates in forced continuous conduction mode (FCCM) under light load conditions. When operating in FCCM, the high side and low side MOSFETs are turned on and off in a complementary fashion and negative inductor current is allowed for part of the switching cycle. The switching frequency remains constant in FCCM.

7.3.9 Output Undervoltage/Overvoltage Protection

The device incorporates an output undervoltage/overvoltage protection (UVP/OVP) circuit to prevent damage to the load. This fault can be triggered during large, fast load transients if insufficient output capacitance is used. The UVP/OVP feature compares the FB pin voltage to internal thresholds. If the FB pin voltage is lower than 90% or greater than 110% of the nominal internal reference voltage, the converter is turned off (i.e. power MOSFETs are turned OFF), a fault is triggered, and the PGOOD pin is pulled low. When the fault hiccup interval is complete, the converter will attempt to restart.

7.3.10 Input Undervoltage/Overvoltage Lockout

The device incorporates an input undervoltage/overvoltage lockout (UVLO/OVLO) circuit. The converter will not operate if the input voltage is below the UVLO threshold. The OVLO circuit protects the converter if the input bus voltage flies higher than the input voltage rating of the device while it is switching. When the input voltage crosses the input rising OVLO trip threshold, the converter turns off all the switches (makes them high impedance) and PGOOD is pulled low. When the input voltage drops lower than the falling OVLO threshold, the converter restarts using the normal soft-start sequence. This feature increases the maximum input voltage the device can sustain without being damaged due to a fault in the system.

7.3.11 Enable and Adjusting Undervoltage Lockout

The EN pin provides electrical on and off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low power state. There is no voltage hysteresis in the EN threshold. The rising and falling voltage thresholds occur at the same level.

The EN pin has an internal hysteretic current source. This allows the user to float the EN pin for self-enabling the device or to design the ON and OFF threshold input voltages with a resistor divider at the EN pin. If an application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin.

The EN pin can be configured as shown in Figure 42. The EN pin has a 1 µA pull-up current i_P which sets the current source value before the start-up sequence. The device includes the second 3 µA current source i_H which is activated when the EN threshold voltage has been exceeded. To achieve clean transitions between the OFF and ON states, it is recommended that the turn OFF threshold is no less than 7.75 V, and the turn ON threshold is no less than 8 V on the VIN pin. It is also recommended to set the UVLO hysteresis to be greater than 500mV in order to avoid repeated chatter during start up or shut down. The value of R_EN(TOP) and R_EN(BOT) can be calculated using Equation 18 and Equation 19 as described in the applications section.

Figure 42. Adjustable VIN Undervoltage Lockout

7.3.12 Series Capacitor Monitoring

The series capacitor voltage is preconditioned and monitored during operation. The series capacitor is located between the source of the high-side MOSFET and the drain of the low-side MOSFET in Phase A . After the input voltage is above UVLO and the EN pin is high, the series capacitor is precharged. A 10 mA current source charges the series capacitor up to half the input voltage. When the series capacitor precharge is complete, the soft start sequence begins. The delay due series capacitor precharge can be calculated using Equation 1.

Equation 1.

Here C_t is the series capacitance, I_pc is the precharge current, and V_IN is the input voltage.

The voltage monitor is continuously tracking the status of the series capacitor. Its function is to ensure the series capacitor voltage, measured differentially between the SCAP pin and the SWA pin, stays within predefined thresholds. These thresholds are relative to the VIN voltage with respect to PGND and set at 35% and 65% of VIN. If the voltage monitor indicates a voltage outside of these thresholds has occurred, a fault is triggered and following actions are taken based on which threshold has been crossed.

7.3.13 Thermal Shutdown

The die temperature is continuously monitored to ensure it is within limits. The thermal shutdown (TSD) fault is triggered when the die temperature exceeds the rising temperature threshold. This interrupts switching by making the switches high impedance. The fault state persists until the die temperature cools down to below the falling temperature threshold. The converter then automatically goes through the normal soft start sequence.

7.3.14 Phase A Power Stage

Phase A implements a bootstrap driver for the high-side MOSFET, an LDO, a low-side driver and a low-side current monitor. Additional logic is included to implement deadtime control and overcurrent protection.

An LDO is implemented to manage the high-side bootstrap driver. This LDO is unique to this topology given the high-side driver is referenced to the SCAP pin and not to the conventional switch node of a buck converter. A conventional bootstrap circuit will not work because the SCAP pin is never connected to PGND during operation. The LDO is designed to produce an output voltage at the VGA pin. This allows a nominal enhancement of around 5V about the VIN rail. The bootstrap capacitor charges when the phase A low side switch is on. An external decoupling capacitor is required on the VGA pin.

The low-side MOSFET current is monitored using a sense FET configuration. This circuit enables the driver to monitor the current delivered in Phase A for overcurrent protection. In the case of overcurrent, a fault flag is set if the current detected exceeds the current limit threshold. Adjustment of this threshold is accomplished via programming the ILIM pin.

7.3.15 Phase B Power Stage

Phase B implements a bootstrap driver for the high-side MOSFET, a low-side driver and a low-side current monitor. Additional logic is included to implement deadtime control and overcurrent protection.

No additional LDO function is required for Phase B as the bootstrap capacitor is charged directly from the VG input rail. A conventional bootstrap circuit is used in phase B.

The overcurrent protection operates in the same manner as Phase A.

7.3.16 Internal Gate Drive Regulator

There is an internal linear regulator that generates a 4.8 V supply rail on the VG+ pin. The input comes from the VIN pin. The VG+ supply rail is used to power the gate drivers of phase A low side switch and phase B switches. It also is the input to another regulator that generates the internal supply rails used by the controller. To improve converter efficiency, an external 5V supply is recommended to be connected to the VG+ pin, thereby overriding the internal 4.8 V regulator. The VG+ supply requires external decoupling capacitance connected between the VG+ and VG- pins. The VG- pin must be connected to AGND and PGND. It is recommended to make this connection directly beneath the device.

7.3.17 Voltage Feed Forward

The input voltage feed forward (VFF) circuit adapts the nominal on-time of the converter in response to changes in the input voltage. The VFF provides a control signal to the on-time generator based on the value of the resistor placed on the TON pin and the input voltage.

7.3.18 Internal Oscillator

The internal oscillator provides a default system clock for the converter. The oscillator can be programmed to run at 4 MHz, 7 MHz, or 10 MHz depending on the resistor connected to the SS/FSEL pin. Synchronization to an external clock is allowed. If provided, an external synchronization clock signal is passed through to the oscillator block and bypasses internal oscillator.

7.3.19 Pulse Frequency Detector

The pulse frequency detector is an important block used to create a phase lock loop (PLL). This portion of the PLL accepts two clock signals and delivers a control signal. The PLL control is held inactive during startup and is activated once soft start is complete. The control signal is delivered to the on-time generator to make small adjustments in the on-time such that the frequency and phase of the switching signals match the reference clock (internal or external SYNC).

7.3.20 On-Time Generator

The on-time generator provides the on-time pulse for high side switches of the converter. The nominal on-time is programmed from the TON pin. The control signal generated by the VFF circuit is proportional to the on-time required by the converter and is adjusted for input voltage variation. Fine adjustment of the on-time comes from pulse frequency detector which enables fixed frequency operation in steady state.