ZHCSMU8C March   2020  – July 2021 TPS54JA20

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO And Using External Bias On VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN For Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3 Control
      8. 7.3.8  Low-side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering The Device From A 12-V Bus
      4. 7.4.4 Powering The Device From A 3.3-V Bus
      5. 7.4.5 Powering The Device From A Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 8.2.2.3  Choose the Inductor
        4. 8.2.2.4  Set the Current Limit (TRIP)
        5. 8.2.2.5  Choose the Output Capacitor
        6. 8.2.2.6  Choose the Input Capacitors (CIN)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance On TI EVM
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

GUID-B4B1F9CA-FF44-427E-9DD9-E91688FA7EE0-low.gifFigure 5-1 RWW Package21-Pin VQFN-HRTop View
GUID-29407A0B-8A15-4974-AD67-49C0172400E4-low.gifFigure 5-2 RWW Package21-Pin VQFN-HRBottom View
Table 5-1 Pin Functions
NO. NAME I/O(1) DESCRIPTION
1 BOOT I/O Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to SW node.
2 AGND G Ground pin, reference point for the internal control circuits
3 TRIP I/O Current limit setting pin. Connect a resistor to AGND to set the current limit trip point. A ±1% tolerance resistor is highly recommended. See Section 7.3.9 for details on OCL setting.
4 MODE I The MODE pin sets the forced continuous-conduction mode (FCCM) or Skip-mode operation. It also selects the operating frequency by connecting a resistor from the MODE pin to the AGND pin. ±1% tolerance resistor is recommended. See Table 7-1 for details.
5 SS/REFIN I/O Dual-function pin. Soft-start function: Connecting a capacitor to VSNS– pin programs soft-start time. Minimum soft-start time (1.5 ms) is fixed internally. A minimum 1-nF capacitor is required for this pin to avoid overshoot during the charge of soft-start capacitor.
REFIN function: The device always looks at the voltage on this SS/REFIN pin as the reference for the control loop. The internal reference voltage can be overridden by an external DC voltage source on this pin for tracking application.
6 VSNS– I The return connection for a remote voltage sensing configuration. It is also used as ground for the internal reference. Short to AGND for single-end sense configuration.
7 FB I Output voltage feedback input. A resistor divider from the VOUT to VSNS– (tapped to FB pin) sets the output voltage.
8 EN I Enable pin. The enable pin turns the DC/DC switching converter on or off. Floating EN pin before start-up disables the converter. The recommended operating condition for EN pin is maximum 5.5 V. Do not connect EN pin to VIN pin directly.
9 PGOOD O Open-drain power-good status signal. When the FB voltage moves outside the specified limits, PGOOD goes low after 2-µs delay.
10, 21 VIN P Power-supply input pins for both integrated power MOSFET pair and the internal LDO. Place the decoupling input capacitors from VIN pins to PGND pins as close as possible.
11, 12, 13, 14, 15, 16, 17, 18 PGND G Power ground of internal low-side MOSFET. At least six PGND vias are required to be placed as close as possible to the PGND pins. This minimizes parasitic impedance and also lowers thermal resistance.
19 VCC I/O Internal 3-V LDO output. An external bias with 3.3-V or higher voltage can be connected to this pin to save the power losses on the internal LDO. The voltage source on this pin powers both the internal circuitry and gate driver. Requires a 2.2-µF, at least 6.3-V rating ceramic capacitor from the VCC pin to PGND pins as the decoupling capacitor and the placement is required to be as close as possible.
20 SW O Output switching terminal of the power converter. Connect this pin to the output inductor.
(1) I = Input, O = Output, P = Supply, G = Ground
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