The TPS54JA20 has an internal 3-V LDO featuring input from VIN and output to VCC. When the EN voltage rises above the enable threshold (typically 1.22 V), the internal LDO is enabled and starts regulating output voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drives.

The VCC pin needs to be bypassed with a 2.2-µF, at least 6.3-V rating ceramic capacitor. An external bias that is above the output voltage of the internal LDO can override the internal LDO. This enhances the efficiency of the converter because the VCC current now runs off this external bias instead of the internal linear regulator.

The VCC UVLO circuit monitors the VCC pin voltage and disables the whole converter when VCC falls below the VCC UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of the device.

The following are considerations when using an external bias on the VCC pin:

• When the external bias is applied on the VCC pin early enough (for example, before EN signal comes in), the internal LDO will be always forced off and the internal analog circuits will have a stable power supply rail at their power enable.
• (Not recommended) When the external bias is applied on the VCC pin late (for example, after EN signal comes in), any power-up and power-down sequencing can be applied as long as there is no excess current pulled out of the VCC pin. It is important to understand that an external discharge path on the VCC pin, which can pull a current higher than the current limit of the internal LDO from the VCC pin and can potentially turn off VCC LDO thereby shutting down the converter output.
• A good power-up sequence is at least one of VIN UVLO rising threshold or EN rising threshold is satisfied later than VCC UVLO rising threshold. For example, a practical power-up sequence is: VIN applied first, then the external bias applied, and then EN signal goes high.