The device monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage events. When the FB voltage becomes lower than 80% of the V_INTREF voltage, the UVP comparator detects and an internal UVP delay counter begins counting. After the 68-µs UVP delay time, the device latches OFF both high-side and low-side FETs drivers. The UVP function enables after the soft start period is complete.

When the FB voltage becomes higher than 116% of the V_INTREF voltage, the OVP comparator detects and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until it reaches a negative current limit, I_NOCL. Upon reaching the negative current limit, the low-side FET is turned off and the high-side FET is turned on again, for the on-time determined by V_IN, V_OUT, and f_SW. The device operates in this cycle until the output voltage is pulled below the UVP threshold voltage for 68 µs. After the 68 µs UVP delay time, both the high-side FET and the low-side FET are latched OFF. The fault is cleared with a reset of VIN or by re-toggling the EN pin.

During the 68-μs UVP delay time, if output voltage becomes higher than UV threshold, thus is not qualified for UV event, the timer will be reset to zero. When the output voltage triggers the UV threshold again, the timer of the 68 μs re-starts.