When an external bias, which is at a different level from the main V_IN bus, is applied onto the VCC pin, the device can be configured to split-rail by utilizing both the main V_IN bus and VCC bias. Connecting a valid VCC bias to VCC pin overrides the internal LDO, thus saves power loss on that linear regulator. This configuration helps to improve overall system level efficiency but requires a valid VCC bias. 3.3-V or 5.0-V rail is the common choice as VCC bias. With a stable VCC bias, the V_IN input range under this configuration can be as low as 2.7 V and up to 16 V.

The noise of the external bias affects the internal analog circuitry. To ensure a proper operation, a clean, low-noise external bias, and good local decoupling capacitor from the VCC pin to PGND pin are required. Figure 7-6 shows an example for this split rail configuration.

The VCC external bias current during nominal operation varies with the bias voltage level and also the operating frequency. For example, by setting the device to skip mode, the VCC pins draw less and less current from the external bias when the frequency decreases under light load condition. The typical VCC external bias current under FCCM operation is listed in the Electrical Characteristics to help you prepare the capacity of the external bias.

Under split rail configuration, VIN, VCC bias, and EN are the signals to enable the part. For start-up sequence, it is recommended that at least one of VIN UVLO rising threshold and EN rising threshold is satisfied later than VCC UVLO rising threshold. A practical start-up sequence example is VIN applied first, then the external bias applied, and then EN signal goes high.

Figure 7-6 Split Rail Configuration With External VCC Bias