ZHCSSS7 august 2023 TPS552872-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
VIN | Input voltage range | 3.0 | 36 | V | ||
VVIN_UVLO | Under voltage lockout threshold | VIN rising | 2.8 | 2.9 | 3.0 | V |
VIN falling | 2.6 | 2.65 | 2.7 | V | ||
IQ | Quiescent current into VIN pin | IC enabled, no load, no switching. VIN = 3.0V to 24V, VOUT = 0.8V, VFB = VREF + 0.1V, RFSW=100kΩ, Tj up to 125°C | 760 | 860 | µA | |
Quiescent current into VOUT pin | IC enabled, no load, no switching, VIN = 3.0V, VOUT = 3V to 20V, VFB = VREF + 0.1V, RFSW=100kΩ, Tj up to 125°C | 760 | 860 | µA | ||
ISD | Shutdown current into VIN pin | IC disabled, VIN = 3.0V to 14V, Tj up to 125°C, EXTVCC pin floating | 0.8 | 3 | µA | |
VCC | Internal regulator output | IVCC = 50mA, VIN = 8V, VOUT = 20V | 5.05 | 5.2 | 5.45 | V |
EN/UVLO | ||||||
VEN_H | EN Logic high threshold | VCC = 3.0V to 5.5V | 1.15 | V | ||
VEN_L | EN Logic low threshold | VCC = 3.0V to 5.5V | 0.4 | V | ||
VEN_HYS | Enable threshold hysteresis | VCC = 3.0V to 5.5V | 0.04 | V | ||
VUVLO | UVLO rising threshold at the EN/UVLO pin | VCC = 3.0V to 5.5V | 1.20 | 1.23 | 1.26 | V |
VUVLO_HYS | UVLO threshold hysteresis | VCC = 3.0V to 5.5V | 10 | mV | ||
IUVLO | Sourcing current at the EN/UVLO pin | VUVLO = 1.3V | 4.4 | 5 | 5.6 | µA |
OUTPUT | ||||||
VOUT | Output voltage range | 0.8 | 22 | V | ||
VOVP | Output overvoltage protection threshold | 22.5 | 23.5 | 24.5 | V | |
VOVP_HYS | Over voltage protection hysteresis | 1 | V | |||
IFB_LKG | Leakage current at FB pin | Tj up to 125°C | 100 | nA | ||
IVOUT_LKG | Leakage current into VOUT pin | IC disabled, VOUT = 20V, VSW2 = 0V, Tj up to 125°C | 1 | 20 | µA | |
REFERENCE VOLTAGE | ||||||
VREF | Reference voltage at the FB pin | 1.188 | 1.2 | 1.212 | V | |
POWER SWITCH | ||||||
RDS(on) | Low-side MOSFET on resistance on buck side | VOUT = 20V, VCC=5.2V | 22 | mΩ | ||
High-side MOSFET on resistance on buck side | VOUT = 20V, VCC=5.2V | 14 | mΩ | |||
Low-side MOSFET on resistance on boost side | VOUT = 20V, VCC=5.2V | 11 | mΩ | |||
High-side MOSFET on resistance on boost side | VOUT = 20V, VCC=5.2V | 11 | mΩ | |||
INTERNAL CLOCK | ||||||
fSW | Switching frequency | RFSW =100k | 180 | 200 | 220 | kHz |
RFSW =8.4k | 2000 | 2200 | 2400 | kHz | ||
tOFF_min | Min. off time | Boost mode | 90 | 145 | ns | |
tON_min | Min. on time | Buck mode | 90 | 130 | ns | |
VFSW | Voltage at FSW pin | 1 | V | |||
CURRENT LIMIT | ||||||
ILIM_AVG | Average inductor current limit | TPS552872-Q1, VIN = 8V, VOUT = 20V, FSW = 400kHz, VCC = 5.2V | 3.3 | 4 | 4.7 | A |
ILIM_PK_H | Peak inductor current limit at high side | TPS552872-Q1, VIN = 8V, VOUT = 20V, FSW = 400kHz | 6.5 | A | ||
ILIM_PK_L | Peak inductor current limit at low side | TPS552872-Q1, VIN = 8V, VOUT = 20V, FSW = 400kHz | 6 | A | ||
VSNS | Current loop regulation voltage between ISP and ISN pin | 48 | 50 | 52 | mV | |
CABLE VOLTAGE DROP COMPENSATION | ||||||
VCDC | Voltage at the CDC pin | RCDC = 20kΩ or floating, VISP – VISN = 50mV | 0.95 | 1 | 1.05 | V |
RCDC = 20kΩ or floating, VISP – VISN = 2mV | 40 | 75 | mV | |||
IFB_CDC | FB pin sinking current | External output feedback, RCDC = 20kΩ, VISP – VISN = 50mV | 7.23 | 7.5 | 7.87 | µA |
External output feedback, RCDC = 20kΩ, VISP – VISN = 0mV | 0 | 0.3 | µA | |||
External output feedback, RCDC = floating, VISP – VISN = 50mV | 0 | 0.3 | µA | |||
ERROR AMPLIFIER | ||||||
ISINK | COMP pin sink current | VFB = VREF + 400mV, VCOMP=1.5V, VCC=5V | 20 | µA | ||
ISOURCE | COMP pin source current | VFB = VREF - 400mV, VCOMP=1.5V, VCC=5V | 60 | µA | ||
VCCLPH | High clamp voltage at the COMP pin | FPWM mode, VOUT = 1.8V to 22V | 1.15 | V | ||
VCCLPL | Low clamp voltage at the COMP pin | FPWM mode | 0.6 | V | ||
GEA | Error amplifier transconductance | 190 | µA/V | |||
SOFT START | ||||||
tSS | Soft-start time | 2.5 | 3.6 | 5 | ms | |
SPREAD SPECTRUM | ||||||
IDITH_CHG | Dithering charge current | VDITH/SYNC = 1.0V; RFSW=49.9kΩ; voltage rising from 0.9V | 2 | µA | ||
IDITH_DIS | Dithering discharge current | VDITH/SYNC = 1.0V; RFSW=49.9kΩ; voltage falling from 1.1V | 2 | µA | ||
VDITH_H | Dither high threshold | 1.07 | V | |||
VDITH_L | Dither low threshold | 0.93 | V | |||
SYNCHRONOUS CLOCK | ||||||
VSNYC_H | Sync clock high voltage threshold | 1.2 | V | |||
VSYNC_L | Sync clock low voltage threshold | 0.4 | V | |||
tSYNC_MIN | Minimum sync clock pulse width | 50 | ns | |||
HICCUP | ||||||
tHICCUP | Hiccup off time | 76 | ms | |||
MODE | ||||||
VMODE | MODE logic high threshold | VCC = 3V to 5.5V | 1.2 | V | ||
VMODE | MODE logic low threshold | VCC = 3V to 5.5V | 0.4 | V | ||
EXTVCC | ||||||
VEXTVCC | EXTVCC Logic high threshold | VCC = 3V to 5.5V | 1.2 | V | ||
VEXTVCC | EXTVCC Logic Low threshold | VCC = 3V to 5.5V | 0.4 | V | ||
Power Good | ||||||
IPG_H | Leakage current into PG pin when outputting high impedance | VPG = 5V | 100 | nA | ||
VPG_L | Output low voltage range of the PG pin | Sinking 4mA current | 0.1 | 0.2 | V | |
Current Limit Indication | ||||||
ICC_H | Leakage current into CC pin when outputting high impedance | VCC = 5 V | 100 | nA | ||
VCC_L | Output low voltage range of the CC pin | Sinking 4-mA current | 0.1 | 0.2 | V | |
PROTECTION | ||||||
TSD | Thermal shutdown threshold | TJ rising | 175 | °C | ||
TSD_HYS | Thermal shutdown hysteresis | TJ falling below Tsd | 20 | °C |