ZHCSSS8 august 2023 TPS552872
PRODUCTION DATA
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | EN/UVLO | I | Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. After the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as programmable UVLO input with 1.23-V internal reference. |
2 | MODE | I | Mode selection pin in light load condition. When it is connected to logic high voltage, the device works in forced PWM mode. When it is connected to logic low voltage, the device works in auto PFM mode. This pin can not be float in application. |
3 | PG | O | Power good indication open drain output. When the output voltage is above 95% of the setting output voltage, this pin outputs high impedance. When the output voltage is below 90% of the setting output voltage, this pin outputs low level |
4 | CC | O | Constant current output indication open drain output. When output current limit is triggered, this pin outputs low level. |
5 | DITH/SYNC | I | Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there is no dithering function. An external clock can be applied at this pin to synchronize the switching frequency. |
6 | FSW | I | The switching frequency is programmed by a resistor between this pin and the AGND pin. |
7 | VIN | PWR | Input of the buck-boost converter. |
8 | SW1 | PWR | The switching node pin of the buck side. It is connected to the drain of the internal buck low-side power MOSFET and the source of internal buck high-side power MOSFET. |
9 | PGND | PWR | Power ground of the IC. |
10 | SW2 | PWR | The switching node pin of the boost side. It is connected to the drain of the internal boost low-side power MOSFET and the source of internal boost high-side power MOSFET. |
11 | VOUT | PWR | Output of the buck-boost converter. |
12 | ISP | I | Positive input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function. |
13 | ISN | I | Negative input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function. |
14 | FB | I | Connect to the center of a resistor divider to program the output voltage |
15 | COMP | O | Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin. |
16 | CDC | O | Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a resistor between this pin and AGND to increase the output voltage to compensate voltage droop across the cable caused by the cable resistance. |
17 | AGND | - | Signal ground of the IC. |
18 | VCC | O | Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this pin and the AGND pin. |
19 | BOOT2 | O | Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1 µF must be connected between this pin and the SW2 pin. |
20 | BOOT1 | O | Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1 µF must be connected between this pin and the SW1 pin. |
21 | EXTVCC | I | Select the internal LDO or external 5V for VCC. When it is connected to logic high voltage or is left floating, select the internal LDO. When it is connected to logic low voltage, select the external 5V for VCC. |