The TPS552882-Q1 has a dual function enable and undervoltage lockout (UVLO) circuit. When the input voltage at the VIN pin is above the input UVLO rising threshold of 3 V and the EN/UVLO pin is pulled above 1.15 V but less than the enable UVLO threshold of 1.23 V, the TPS552882-Q1 is enabled but still in standby mode. The TPS552882-Q1 starts to detect the resistance between the MODE pin and ground. After that, the TPS55288x selects the power supply for V_CC and the PFM or FPWM mode for light load condition accordingly.

The EN/UVLO pin has an accurate UVLO voltage threshold to support programmable input undervoltage lockout with hysteresis. When the EN/UVLO pin voltage is greater than the UVLO threshold of 1.23 V, the TPS552882-Q1 is enabled for switching operation. A hysteresis current I_{UVLO_HYS} of 5 μA is sourced out of the EN/UVLO pin to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly changing input voltage.

By using resistor divider as shown in Figure 7-1, the turnon threshold is calculated using Equation 1.

Equation 1.

where

• V_UVLO is the UVLO threshold of 1.23 V at the EN/UVLO pin

The hysteresis between the UVLO turnon threshold and turnoff threshold is set by the upper resistor in the EN/UVLO resistor divider and is given by the Equation 2.

Equation 2.

where

• I_{UVLO_HYS} is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above V_UVLO

Figure 7-1 Programmable UVLO With Resistor Divider at the EN/UVLO Pin

Using an NMOS FET together with resistor divider can implement both logic enable and programmable UVLO as shown in Figure 7-2. The EN logic high level must be greater than enable threshold plus the V_th of the NMOSFET Q1. The Q1 also eliminates the leakage current from VIN to ground through the UVLO resistor divider during shutdown mode.

Figure 7-2 Logic Enable and Programmable UVLO