ZHCSMV3A December 2020 – December 2021 TPS552882-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VCC Power Supply
- 7.3.2 Operation Mode Setting
- 7.3.3 Input Undervoltage Lockout
- 7.3.4 Enable and Programmable UVLO
- 7.3.5 Soft Start
- 7.3.6 Shutdown
- 7.3.7 Switching Frequency
- 7.3.8 Switching Frequency Dithering
- 7.3.9 Inductor Current Limit
- 7.3.10 Internal Charge Path
- 7.3.11 Output Voltage Setting
- 7.3.12 Output Current Indication and Cable Voltage Drop Compensation
- 7.3.13 Integrated Gate Drivers
- 7.3.14 Output Current Limit
- 7.3.15 Overvoltage Protection
- 7.3.16 Output Short Circuit Protection
- 7.3.17 Thermal Shutdown
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
8.2.2.8 Loop Stability
The TPS55288 uses average current control scheme. The inner current loop uses internal compensation and requires the inductor value must be larger than 1.2/fSW. The outer voltage loop requires an external compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation network comprised of resistor and ceramic capacitors is connected to the COMP pin.
The TPS55288 operates in buck mode or boost mode. Therefore, both buck and boost operating modes require loop compensations. The restrictive one of both compensations is selected as the overall compensation from a loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the boost mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ).
The power stage in boost mode can be modeled by Equation 19.
where
- RLOAD is the output load resistance
- D is the switching duty cycle in boost mode
- RSENSE is the equivalent internal current sense resistor, which is 0.055 Ω
The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use Equation 20 to Equation 22 to calculate them.
The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the control portion of the loop. The transfer function of the control portion is shown by Equation 23.
where
- GEA is the transconductance of the error amplifier
- REA is the output resistance of the error amplifier
- VREF is the reference voltage input to the error amplifier
- VOUT is the output voltage
- fCOMP1 and fCOMP2 are the pole’s frequency of the compensation network
- fCOMZ is the zero’s frequency of the compensation network
The total open-loop gain is the product of GPS(s) and GC(s). The next step is to choose the loop crossover frequency, fC, at which the total open-loop gain is 1, namely 0 dB. The higher in frequency that the loop gain stays above 0 dB before crossing over, the faster the loop response. It is generally accepted that the loop gain cross over 0 dB at the frequency no higher than the lower of either 1/10 of the switching frequency, fSW or 1/5 of the RHPZ frequency, fRHPZ.
Then, set the value of RC, CC and CP by Equation 24 to Equation 26.
where
- fC is the selected crossover frequency
If the calculated CP is less than 10 pF, it can be left open.
Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output voltage ringing during the line and load transient.