7.3.1 Voltage Reference

The 600-mV bandgap cell is internally connected to the non-inverting input of the error amplifier. The reference voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final regulation voltage. The 1% tolerance on the reference voltage allows the user to design a very accurate power supply.

Figure 19. Startup Sequence and Timing

7.3.2 Enable Functionality, Startup Sequence and Timing

After input power is applied, an internal 40-μA current source begins to charge the soft-start capacitor connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal BP regulator followed by a calibration. Total calibration time is approximately 1.9 ms. See Figure 19. During the calibration, the device performs the following two functions.

7.3.3 Soft-Start Time

The soft-start time of the TPS56121 is user programmable by selecting a single capacitor. The EN/SS pin sources 10 μA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the 10 μA to charge the capacitor through a 600 mV range. There is some initial lag due to calibration and an offset (800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier.

The soft-start is accomplished in a closed-loop, meaning that the error amplifier controls the output voltage at all times during the soft-start period and the feedback loop is never open as occurs in duty cycle limit soft-start schemes. The error amplifier has two non-inverting inputs, one connected to the 600-mV reference voltage, and the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier controls the FB pin to. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800 mV offset voltage plus the 600 mV reference voltage), the 600-mV reference voltage becomes the dominant input and the converter has reached its final regulation voltage.

The capacitance required for a given soft-start ramp time for the output voltage is calculated in Equation 1.

Equation 1.

where

• C_SS is the required capacitance on the EN/SS pin (nF)
• I_SS is the soft-start source current (10 μA)
• V_FB is the feedback reference voltage (0.6 V)
• t_SS is the desired soft-start ramp time (ms)

7.3.4 Oscillator

The oscillator frequency is internally fixed at 500 KHz if there is no resistor connected from COMP pin to GND. Optionally, a 40.2-kΩ resistor from the COMP pin to GND sets the frequency to 300 KHz. Alternatively, a 13.3-kΩ resistor from COMP pin GND sets the frequency to 1 MHz.

7.3.5 Overcurrent Protection (OCP)

Programmable OCP level at ILIM is from 6 mV to 50 mV. With a scale factor of 2, the actual OC trip point across the low-side FET is in the range of 12 mV to 100 mV.

If the voltage drop across R_OCSET reaches 300 mV during calibration (No R_OCSET resistor included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing.

OCP level for the high-side FET is fixed at 34 A (typical). The high-side OCP provides pulse-by-pulse current limiting.

OCP sensing for the low-side FET is a true inductor valley current detection, using sample and hold. Equation 2 can be used to calculate R_OCSET. Since the TPS56121 is designed for 15-A full-Load current and not intentionally designed for an OCP level below 10 A, use an R_OCSET value above 1 kΩ to get an accurate OCP tripping point.

Equation 2.

where

• I_P-P is the peak-to-peak inductor current (A)
• I_OUT(max) is the trip point for OCP (A)
• R_OCSET is the resistor used for setting the OCP level (Ω)

An overcurrent (OC) condition is detected by sensing voltage drop across the low-side FET and across the high-side FET. If the voltage drop across either FET exceeds OC threshold, a count increments one count. If no OC condition is detected on either FET, the fault counter decrements by one counter. If three OC pulses are summed, a fault condition is declared which cycles the soft-start function in a hiccup mode. Hiccup mode is defined as four dummy soft-start timeouts followed by a real one if overcurrent condition is encountered during normal operation; or five dummy soft-start timeouts followed by a real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until the fault condition is removed.

7.3.6 Switching Node (SW)

The SW pin connects to the switching node of the power conversion stage. It acts as the return path for the high-side gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the output capacitance (C_OSS) of both power FETs form a resonant circuit that can produce high frequency ( > 100 MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the pin.

In many cases, a series resistor and capacitor snubber network connected from the switching node to PGND can be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber network components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin exceeds the limit, then include snubber components.

Placing a BOOT resistor with a value between 5 Ω and 15 Ω in series with the BOOT capacitor slows down the turn-on of the high-side FET and can help to reduce the peak ringing at the switching node as well.

7.3.7 Input Undervoltage Lockout (UVLO)

The TPS56121 has fixed input UVLO. In order for the device to turn on, the following conditions must be met:

• the EN/SS pin voltage must be greater than V_IH
• the input voltage must exceed UVLO on voltage V_UVLO

The UVLO has a minimum of 500 mV hysteresis built-in.

7.3.8 Pre-Bias Startup

The TPS56121 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. There are no PWM pulses until the internal soft-start voltage rises above the error amplifier input (FB pin), if the output is pre-biased. Once the soft-start voltage exceeds the error amplifier input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow on time. It then increments the on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.

This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage startup and ramp to regulation is smooth and controlled.

7.3.9 Power Good

The TPS56121 provides an indication that output is good for the converter. This is an open drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include:

• V_FB is more than ±12.5% from nominal
• soft-start is active
• a short circuit condition has been detected

7.3.10 Thermal Shutdown

If the junction temperature of the device reaches the thermal shutdown limit of 145°C, both the high-side FET and low-side FET maintain off status. When the junction cools to the required level (125°C typical), the PWM initiates soft start as during a normal power-up cycle.