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ZHCS124C MARCH 2011 – January 2015 TPS56221

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DQP|22

散热焊盘机械数据 (封装 | 引脚)

DQP|22
- QFND267C

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Voltage	VDD, VIN	–0.3	16.5	V
	SW	–3	25
	SW (< 100 ns pulse width, 10 µJ)	–5
	BOOT	–0.3	30
	BOOT-SW (differential from BOOT to SW)	–0.3	7
	COMP, PGOOD, FB, BP, EN/SS, ILIM	–0.3	7
Junction Temperature, T_J		–40	150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those included under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_DD	VIN Input voltage	4.5		14	V
T_J	Operating junction temperature	–40		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS56221	UNIT
		PQFN
		22 PINS
R_θJA	Junction-to-ambient thermal resistance	34.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	22.9
ψ_JT	Junction-to-top characterization parameter	0.6
ψ_JB	Junction-to-board characterization parameter	5.0
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

–40°C ≤ T_J ≤ 125°C, V_VDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOLTAGE REFERENCE
V_FB	FB input voltage	T_J = 25°C, 4.5 V ≤ V_VDD ≤ 14 V	597	600	603	mV
V_FB	FB input voltage	–40°C ≤ T_J ≤ 125°C, 4.5 V ≤ V_VDD ≤ 14 V	594	600	606	mV
INPUT SUPPLY
V_VDD	Input supply voltage range		4.5		14	V
IVDD_SD	Shutdown supply current	V_EN/SS = 0.2 V		80	120	µA
IVDD_Q	Quiescent, nonswitching	Let EN/SS float, V_FB = 1 V		2.5	5.0	mA
V_UVLO	UVLO ON Voltage		4.0		4.3	V
V_UVLO(HYS)	UVLO hysteresis		500		700	mV
ENABLE/SOFT-START
V_IH	High-level input voltage, EN/SS		0.55	0.70	1.00	V
V_IL	Low-level input voltage, EN/SS		0.27	0.30	0.33	V
I_SS	Soft-start source current		8	10	12	µA
V_SS	Soft-start voltage level – start of ramp		0.4	0.8	1.3	V
BP REGULATOR
V_BP	Output voltage	I_BP = 10 mA	6.2	6.5	6.8	V
V_DO	Regulator dropout voltage, V_VDD – V_BP	I_BP = 25 mA, V_VDD = 4.5 V		70	125	mV
OSCILLATOR
f_SW	Switching frequency	R_COMP = 40.2 kΩ, 4.5 V ≤ V_VDD ≤ 14 V	270	300	330	kHz
		R_COMP = open, 4.5 V ≤ V_VDD ≤ 14 V	450	500	550	kHz
		R_COMP = 13.3 kΩ, 4.5 V ≤ V_VDD ≤ 14 V	0.8	0.95	1.1	MHz
V_RAMP⁽¹⁾	Ramp amplitude		V_VDD/6.6	V_VDD/6	V_VDD/5.4	V
PWM
D_MAX⁽¹⁾	Maximum duty cycle	f_sw = 300 kHz, V_FB = 0 V, 4.5 V ≤ V_VDD ≤ 14 V	93%
		f_sw = 500 kHz, V_FB = 0 V, 4.5 V ≤ V_VDD ≤ 14 V	90%
		f_sw = 1 MHz, V_FB = 0 V, 4.5 V ≤ V_VDD ≤ 14 V	85%
t_ON(min)⁽¹⁾	Minimum controllable pulse width				100	ns
ERROR AMPLIFIER
GBWP ⁽¹⁾	Gain bandwidth product		10	24		MHz
A_OL ⁽¹⁾	Open loop gain		60			dB
I_IB	Input bias current (current out of FB pin)	V_FB = 0.6 V			75	nA
I_EAOP	Output source current	V_FB = 0 V	1.5			mA
I_EAOM	Output sink current	V_FB = 1 V	1.5			mA
POWER GOOD
V_OV	Feedback upper voltage limit for PGOOD		655	675	700	mV
V_UV	Feedback lower voltage limit for PGOOD		500	525	550	mV
V_PGD-HYST	PGOOD hysteresis voltage at FB			30	45	mV
R_PGD	PGOOD pull down resistance	V_FB = 0 V, I_FB = 5 mA		30	70	Ω
I_PGDLK	PGOOD leakage current	550 mV < V_FB < 655 mV, V_PGOOD = 5 V		10	20	µA
OUTPUT STAGE
R_HI	High-side device resistance	T_J = 25°C, (V_BOOT– V_SW) = 5.5 V		4.5	6.5	mΩ
R_LO	Low side device resistance	T_J = 25°C		1.9	2.7	mΩ
OVERCURRENT PROTECTION (OCP)
t_PSSC(min)⁽¹⁾	Minimum pulse time during short circuit			250		ns
t_BLNKH⁽¹⁾	Switch leading-edge blanking pulse time (high-side detection)			150		ns
I_OCH	OC threshold for high-side FET	T_J = 25°C, (V_BOOT– V_SW) = 5.5 V	45	54	65	A
I_ILIM	ILIM current source	T_J = 25°C		10.0		µA
V_OCLPRO⁽¹⁾	Programmable OC range for low side FET	T_J = 25°C	12		100	mV
t_OFF	OC retry cycles on EN/SS pin			4		Cycle
BOOT DIODE
V_DFWD	Bootstrap diode forward voltage	I_BOOT = 5 mA		0.8		V
THERMAL SHUTDOWN
T_JSD⁽¹⁾	Junction shutdown temperature			145		ºC
T_JSDH⁽¹⁾	Hysteresis			20		ºC

(1) Ensured by design. Not production tested

6.6 Typical Characteristics

Figure 13 to Figure 18 are measured on a 2.5 inch × 2.5 inch, 0.062 inch thick FR4 board with 4 layers and 2-oz. copper, a 0.32-µH output inductor and a DCR of 0.32 mΩ.