The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by input voltage, output voltage, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current I_OUT. If the measured drain-to-source voltage of the low-side FET is above the voltage proportional to current limit, the low-side FET stays on until the current level becomes lower than the OCL level which reduces the output current available. When the current is limited the output voltage tends to drop because the load demand is higher than what the converter can support. When the output voltage falls below 68% of the target voltage, the UVP comparator detects it and shuts down the device after a wait time of 1 ms, the device re-starts after a hiccup time of 7 ms. In this type of valley detect control, the load current is higher than the OCL threshold by one half of the peak-to-peak inductor ripple current. When the overcurrent condition is removed, the output voltage returns to the regulated value. If an OCL condition happens during start-up, then the device enters hiccup-mode immediately without a wait time of 1 ms.