The RT/CLK pin synchronizes the converter to an external system clock. See Figure 7-9. To implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75 ns. If the pin goes above the PLL upper threshold, a mode change occurs, and the pin becomes a synchronization input. The device disables the internal amplifier, and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, the device re-enables the internal amplifier and the mode returns to the frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V, typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of PH synchronizes to the falling edge of the RT/CLK pin.

Figure 7-9 Synchronizing to a System Clock

Figure 7-10 Plot of Synchronizing to System Clock