7.3.19 Simple Small-Signal Model for Peak-Current-Mode Control

Figure 40 describes a simple small-signal model that the designer can use to understand how to design the frequency compensation. The designer can approximate the TPS57140-EP power stage by a voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor. Equation 10 shows the control-to-output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 39) is the power-stage transconductance. The gm_PS for the TPS57140-EP is 6 S. The low-frequency gain of the power-stage frequency response is the product of the transconductance and the load resistance as shown in Equation 11.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 12). The combined effect is highlighted by the dashed line in the right half of Figure 40. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions, which makes it easier to design the frequency compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency-compensation design. Using high-ESR aluminum electrolytic capacitors may reduce the number of frequency-compensation components needed to stabilize the overall loop because the phase margin increases from the ESR zero at the lower frequencies (see Equation 13).

Figure 40. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control

Equation 10.

Equation 11.

Equation 12.

Equation 13.