ZHCSOQ1D october 2022 – september 2023 TPS61033 , TPS610333
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
VIN | Input voltage range | 1.8 | 5.5 | V | ||
VIN_UVLO | Under-voltage lockout threshold | VIN rising | 1.7 | 1.79 | V | |
VIN falling | 1.6 | V | ||||
VIN_HYS | VIN UVLO hysteresis | 65 | mV | |||
IQ | Quiescent current into VIN pin | IC enabled, No load, No switching VIN = 1.8 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 125°C | 13 | 20 | 25 | µA |
Quiescent current into VOUT pin | IC enabled, No load, No switching VOUT = 2.2 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 125°C | 5.3 | 9 | µA | ||
ISD | Shutdown current into VIN and SW pin | IC disabled, VIN = VSW = 3.6 V, TJ = 25°C | 0.1 | 0.2 | µA | |
OUTPUT | ||||||
VOUT | Output voltage setting range | 2.2 | 5.5 | V | ||
VOUT (fixed 5V) | Fixed output voltage | FB connected to VIN VIN < VOUT, PWM mode |
4.93 | 5 | 5.07 | V |
VREF | Reference voltage at the FB pin | PWM mode | 591 | 600 | 609 | mV |
VREF | Reference voltage at the FB pin | PFM mode | 606 | mV | ||
VOVP | Output over-voltage protection threshold | VOUT rising | 5.5 | 5.75 | 6.0 | V |
VOVP_HYS | Over-voltage protection hysteresis | 0.11 | V | |||
IFB_LKG | Leakage current at FB pin | TJ = 25°C | 4 | 25 | nA | |
IFB_LKG | Leakage current at FB pin | TJ = 125°C | 5 | 30 | nA | |
IVOUT_LKG | Leakage current into VOUT pin | IC disabled, VIN = 0 V, VSW = 0 V, VOUT = 5.5 V, TJ = 25°C | 0.2 | 0.5 | µA | |
tss | Soft startup time | Internal SS ramp time | 0.86 | ms | ||
POWER SWITCH | ||||||
RDS(on) | High-side MOSFET on resistance | VOUT = 5.0 V | 46 | mΩ | ||
RDS(on) | Low-side MOSFET on resistance | VOUT = 5.0 V | 25 | mΩ | ||
fSW | Switching frequency | VIN = 3.6 V, VOUT = 5.0 V, PWM mode | 2.0 | 2.4 | 2.8 | MHz |
tON_min | Minimum on time | 20 | 48 | 65 | ns | |
tOFF_min | Minimum off time | 35 | 70 | ns | ||
ILIM_SW | Valley current limit | VIN = 3.6 V, VOUT = 5.0 V TPS61033 | 4.7 | 5.5 | 6.1 | A |
ILIM_SW | Valley current limit | VIN = 3.6 V, VOUT = 5.0 V TPS610333 | 1.55 | 1.85 | 2.25 | A |
IREVERSE | Reverse current limit (MODE=1) | VIN = 3.6 V, VOUT = 5.0 V; MODE = 1 | -1.4 | A | ||
ILIM_CHG | Pre-charge current | VIN = 1.8 - 5.5 V, VOUT < 0.4 V | 330 | mA | ||
ILIM_CHG_max | Maximum pre-charge current | VIN = 2.4 V, VOUT > 0.4 V ; TPS610333 | 800 | 1100 | mA | |
LOGIC INTERFACE | ||||||
VEN_H | EN logic high threshold | VIN > 1.8 V or VOUT > 2.2 V | 1.2 | V | ||
VEN_L | EN logic low threshold | VIN > 1.8 V or VOUT > 2.2 V | 0.4 | V | ||
VMODE_H | MODE Logic high threshold | VIN > 1.8 V or VOUT > 2.2 V | 1.2 | V | ||
VMODE_L | MODE Logic Low threshold | VIN > 1.8 V or VOUT > 2.2 V | 0.4 | V | ||
RDOWN | EN pins internal pull-down resistor | 10 | MΩ | |||
RDOWN | MODE pins internal pull-down resistor | 1 | MΩ | |||
POWER GOOD | ||||||
PGDOV | PGOOD upper threshold | % of VOUT setting | 105 | 107 | 110 | % |
PGDUV | PGOOD lower threshold | % of VOUT setting | 91 | 93 | 95 | % |
PGDHYST | PGOOD upper threshold (rising&falling) | % of VOUT setting | 2.5 | % | ||
tPGDFLT(rise) | Delay time to PGOOD high signal | 1.3 | ms | |||
tPGDFLT(fall) | Glitch filter time of PGOOD | 33 | µs | |||
PROTECTION | ||||||
TSD | Thermal shutdown threshold | TJ rising | 170 | °C | ||
TSD | Thermal shutdown threshold | TJ falling | 155 | °C | ||
TSD_HYS | Thermal shutdown hysteresis | TJ falling below TSD | 15 | °C |