ZHCSJH2E November 2007 – April 2019 TPS61165
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Device Options
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
- DRV|6
订购信息
9.2.1.2.4 EasyScale: One-Wire Digital Dimming
EasyScale is a simple but flexible one-pin interface to configure the FB voltage. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 11 and Table 4 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale compared with other on-pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7 kBit/sec and up to 160 kBit/sec.
Table 3. Selectable FB Voltage
| FB Voltage (mV) | D4 | D3 | D2 | D1 | D0 | |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 5 | 0 | 0 | 0 | 0 | 1 |
| 2 | 8 | 0 | 0 | 0 | 1 | 0 |
| 3 | 11 | 0 | 0 | 0 | 1 | 1 |
| 4 | 14 | 0 | 0 | 1 | 0 | 0 |
| 5 | 17 | 0 | 0 | 1 | 0 | 1 |
| 6 | 20 | 0 | 0 | 1 | 1 | 0 |
| 7 | 23 | 0 | 0 | 1 | 1 | 1 |
| 8 | 26 | 0 | 1 | 0 | 0 | 0 |
| 9 | 29 | 0 | 1 | 0 | 0 | 1 |
| 10 | 32 | 0 | 1 | 0 | 1 | 0 |
| 11 | 35 | 0 | 1 | 0 | 1 | 1 |
| 12 | 38 | 0 | 1 | 1 | 0 | 0 |
| 13 | 44 | 0 | 1 | 1 | 0 | 1 |
| 14 | 50 | 0 | 1 | 1 | 1 | 0 |
| 15 | 56 | 0 | 1 | 1 | 1 | 1 |
| 16 | 62 | 1 | 0 | 0 | 0 | 0 |
| 17 | 68 | 1 | 0 | 0 | 0 | 1 |
| 18 | 74 | 1 | 0 | 0 | 1 | 0 |
| 19 | 80 | 1 | 0 | 0 | 1 | 1 |
| 20 | 86 | 1 | 0 | 1 | 0 | 0 |
| 21 | 92 | 1 | 0 | 1 | 0 | 1 |
| 22 | 98 | 1 | 0 | 1 | 1 | 0 |
| 23 | 104 | 1 | 0 | 1 | 1 | 1 |
| 24 | 116 | 1 | 1 | 0 | 0 | 0 |
| 25 | 128 | 1 | 1 | 0 | 0 | 1 |
| 26 | 140 | 1 | 1 | 0 | 1 | 0 |
| 27 | 152 | 1 | 1 | 0 | 1 | 1 |
| 28 | 164 | 1 | 1 | 1 | 0 | 0 |
| 29 | 176 | 1 | 1 | 1 | 0 | 1 |
| 30 | 188 | 1 | 1 | 1 | 1 | 0 |
| 31 | 200 | 1 | 1 | 1 | 1 | 1 |
Figure 11. EasyScale Protocol Overview Table 4. EasyScale Bit Description
| BYTE | BIT NUMBER | NAME | TRANSMISSION DIRECTION | DESCRIPTION |
|---|---|---|---|---|
| Device Address Byte
72 hex |
7 | DA7 | IN | 0 MSB device address |
| 6 | DA6 | 1 | ||
| 5 | DA5 | 1 | ||
| 4 | DA4 | 1 | ||
| 3 | DA3 | 0 | ||
| 2 | DA2 | 0 | ||
| 1 | DA1 | 1 | ||
| 0 | DA0 | 0 LSB device address | ||
| Data byte | 7 (MSB) | RFA | IN | Request for acknowledge. If high, acknowledge is applied by device |
| 6 | A1 | 0 Address bit 1 | ||
| 5 | A0 | 0 Address bit 0 | ||
| 4 | D4 | Data bit 4 | ||
| 3 | D3 | Data bit 3 | ||
| 2 | D2 | Data bit 2 | ||
| 1 | D1 | Data bit 1 | ||
| 0 (LSB) | D0 | Data bit 0 | ||
| ACK | OUT | Acknowledge condition active 0, this condition is only applied in case RFA bit is set. Open drain output, line must be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open-drain output stage. In case of a push-pull output stage Acknowledge condition may not be requested! |
Figure 12. EasyScale — Bit Coding All bits are transmitted MSB first and LSB last. Figure 12 shows the protocol without acknowledge request (Bit RFA = 0), Figure 12 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (2 μs) before the bit transmission starts with the falling edge. If the CTRL pin is already at a high level, no start condition is needed prior to the device address byte. The transmission of each byte is closed with an End of Stream condition for at least tEOS (2 μs).
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and tHIGH. It can be simplified to:
High Bit: tHIGH > tLOW, but with tHIGH at least 2x tLOW, see Figure 12.
Low Bit: tHIGH < tLOW, but with tLOW at least 2x tHIGH, see Figure 12.
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on the relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
- Acknowledge is requested by a set RFA bit.
- The transmitted device address matches with the device address of the device.
- 16 bits is received correctly.
If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512 μs maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master controller keeps the line low in this period. The master device can detect the acknowledge condition with its input by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the acknowledge condition ends.
The acknowledge condition may be requested only if the master device has an open drain output. For a push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500 μA is recommended to for such cases as:
- accidentally requested acknowledge, or
- to protect the internal ACKN-MOSFET.