ZHCSG87E February 2017 – August 2019 TPS61178
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Under-voltage Lockout
- 8.3.2 Enable and Disable
- 8.3.3 Startup
- 8.3.4 Load Disconnect Gate Driver
- 8.3.5 Adjustable Peak Current Limit
- 8.3.6 Output Short Protection (with load disconnected FET)
- 8.3.7 Adjustable Switching Frequency
- 8.3.8 External Clock Synchronization (TPS611781)
- 8.3.9 Error Amplifier
- 8.3.10 Slope Compensation
- 8.3.11 Start-up with the Output Pre-Biased
- 8.3.12 Bootstrap Voltage (BST)
- 8.3.13 Over-voltage Protection
- 8.3.14 Thermal Shutdown
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.3 Setting the Current Limit
- 9.2.4 Setting the Output Voltage
- 9.2.5 TPS61178 Application Waveform
- 9.3 System Examples
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
9.3.3 TPS611781 External Clock Synchronization
The Figure 35 is the typical application schematic for synchronized by an external clock of 2.2 MHz. It is for the Forced PWM mode operation to avoid the noise-sensitive frequency range, for instance the audible noise and AM band.
Figure 35. 16-V Output Voltage Synchronized by 2.2 MHz External Clock